int
phy_RF6052_Config_ParaFile(
IN PADAPTER Adapter
)
{
u32 u4RegValue;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
static char sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A;
static char sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B;
static char sz92CRadioAFile[] = RTL8192C_PHY_RADIO_A;
static char sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B;
static char sz88CTestRadioAFile[] = RTL8188C_PHY_RADIO_A;
static char sz88CTestRadioBFile[] = RTL8188C_PHY_RADIO_B;
static char sz92CTestRadioAFile[] = RTL8192C_PHY_RADIO_A;
static char sz92CTestRadioBFile[] = RTL8192C_PHY_RADIO_B;
static char sz92DRadioAFile[] = RTL8192D_PHY_RADIO_A;
static char sz92DRadioBFile[] = RTL8192D_PHY_RADIO_B;
static char sz92DTestRadioAFile[] = RTL8192D_PHY_RADIO_A;
static char sz92DTestRadioBFile[] = RTL8192D_PHY_RADIO_B;
u8 *pszRadioAFile, *pszRadioBFile;
u8 u1bTmp;
BOOLEAN bMac1NeedInitRadioAFirst = _FALSE;
BOOLEAN bNeedPowerDownRadioA = _FALSE;
// 92D RF config zhiyuan 2010/04/07
// Single phy mode: use radio_a radio_b config path_A path_B seperately by MAC0, and MAC1 needn't configure RF;
// Dual PHY mode:MAC0 use radio_a config 1st phy path_A, MAC1 use radio_b config 2nd PHY path_A.
if(IS_HARDWARE_TYPE_8192D(pHalData)){
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz92DRadioAFile;
pszRadioBFile = sz92DRadioBFile;
if(pHalData->interfaceIndex==1)
{
if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY)
pszRadioAFile = sz92DRadioBFile;
else
return rtStatus;
}
}
else
{
pszRadioAFile = sz92DTestRadioAFile;
pszRadioBFile = sz92DTestRadioBFile;
if(pHalData->interfaceIndex==1)
{
//
// when 92D test chip dual mac dual phy mode, if enable MAC1 first, before init RF radio B,
// also init RF radio A, and then let radio A go to power down mode.
// Note: normal chip need do this or not will be considerred later.
//
if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY)
{
u1bTmp = read8(Adapter, REG_MAC0);
if (!(u1bTmp&MAC0_ON))
{
// MAC0 not enabled, also init radio A before init radio B.
// Enable BB and RF
#if (DEV_BUS_TYPE == PCI_INTERFACE)
//PlatformEFIOWrite1Byte(Adapter, REG_SYS_FUNC_EN, 0xE0);
#if 0
MpWritePCIDwordDBI8192C(Adapter,
(REG_SYS_FUNC_EN - 2),
MpReadPCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), BIT3)&0xFFFCFFFF,
BIT3);
#endif
//u2bTmp = PlatformEFIORead2Byte(Adapter, REG_SYS_FUNC_EN);
//PlatformEFIOWrite2Byte(Adapter, REG_SYS_FUNC_EN, u2bTmp|BIT13|BIT0|BIT1);
MpWritePCIDwordDBI8192C(Adapter,
(REG_SYS_FUNC_EN - 2),
MpReadPCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), BIT3)|BIT29|BIT16|BIT17,
BIT3);
#elif (DEV_BUS_TYPE == USB_INTERFACE)
pHalData->bDuringMac1InitRadioA = _TRUE;
write16(Adapter, REG_SYS_FUNC_EN, read16(Adapter, REG_SYS_FUNC_EN)&0xFFFC);
write16(Adapter, REG_SYS_FUNC_EN, read16(Adapter, REG_SYS_FUNC_EN)|BIT13|BIT0|BIT1);
pHalData->bDuringMac1InitRadioA = _FALSE;
#endif
pHalData->NumTotalRFPath = 2;
bMac1NeedInitRadioAFirst = _TRUE;
}
else
{
// MAC0 enabled, only init radia B.
pszRadioAFile = sz92DTestRadioBFile;
}
}
else
{
return rtStatus;
}
}
}
}
else{
if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz92CRadioAFile;
pszRadioBFile = sz92CRadioBFile;
}
else
{
pszRadioAFile = sz92CTestRadioAFile;
pszRadioBFile = sz92CTestRadioBFile;
}
}
else
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz88CRadioAFile;
pszRadioBFile = sz88CRadioBFile;
}
else
{
pszRadioAFile = sz88CTestRadioAFile;
pszRadioBFile = sz88CTestRadioBFile;
}
}
}
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
if (IS_HARDWARE_TYPE_8192D(pHalData) && bMac1NeedInitRadioAFirst)
{
if (eRFPath == RF90_PATH_A)
{
pHalData->bDuringMac1InitRadioA = _TRUE;
bNeedPowerDownRadioA = _TRUE;
}
if (eRFPath == RF90_PATH_B)
{
pHalData->bDuringMac1InitRadioA = _FALSE;
bMac1NeedInitRadioAFirst = _FALSE;
eRFPath = RF90_PATH_A;
pszRadioAFile = sz92DTestRadioBFile;
pHalData->NumTotalRFPath = 1;
}
}
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF90_PATH_B :
case RF90_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
udelay_os(1);//PlatformStallExecution(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
udelay_os(1);//PlatformStallExecution(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF90_PATH_A:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B :
case RF90_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
goto phy_RF6052_Config_ParaFile_Fail;
}
}
if (IS_HARDWARE_TYPE_8192D(pHalData) && bNeedPowerDownRadioA)
{
// check MAC0 enable or not again now, if enabled, not power down radio A.
u1bTmp = read8(Adapter, REG_MAC0);
if (!(u1bTmp&MAC0_ON))
{
// power down RF radio A according to YuNan's advice.
#if (DEV_BUS_TYPE == PCI_INTERFACE)
MpWritePCIDwordDBI8192C(Adapter,
rFPGA0_XA_LSSIParameter,
0x00000000,
BIT3);
#elif (DEV_BUS_TYPE == USB_INTERFACE)
pHalData->bDuringMac1InitRadioA = _TRUE;
write32(Adapter, rFPGA0_XA_LSSIParameter, 0x00000000);
pHalData->bDuringMac1InitRadioA = _FALSE;
#endif
}
bNeedPowerDownRadioA = _FALSE;
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
u8 usb_hal_bus_init(_adapter * padapter)
{
u8 val8 = 0;
u8 ret;
u8 PollingCnt = 20;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
ret =_SUCCESS;
RT_TRACE(_module_hci_hal_init_c_, _drv_info_,("chip_version=%d\n", pregistrypriv->chip_version));
//pregistrypriv->chip_version = RTL8712_2ndCUT;//RTL8712_1stCUT;
if(pregistrypriv->chip_version == RTL8712_FPGA)
{
val8 = 0x01;
write8(padapter, SYS_CLKR, val8);//switch to 80M clock
val8 = read8(padapter, SPS1_CTRL);
val8 = val8 |0x01;
write8(padapter, SPS1_CTRL, val8);//enable VSPS12 LDO Macro block
val8 = read8(padapter, AFE_MISC);
val8 = val8 |0x01;
write8(padapter, AFE_MISC, val8);//Enable AFE Macro Block's Bandgap
val8 = read8(padapter, LDOA15_CTRL);
val8 = val8 |0x01;
write8(padapter, LDOA15_CTRL, val8);//enable LDOA15 block
val8 = read8(padapter, SPS1_CTRL);
val8 = val8 |0x02;
write8(padapter, SPS1_CTRL, val8);//Enable VSPS12_SW Macro Block
val8 = read8(padapter, AFE_MISC);
val8 = val8 |0x02;
write8(padapter, AFE_MISC, val8);//Enable AFE Macro Block's Mbias
val8 = read8(padapter, SYS_ISO_CTRL+1);
val8 = val8 |0x08;
write8(padapter, SYS_ISO_CTRL+1, val8);//isolate PCIe Analog 1.2V to PCIe 3.3V and PCIE Digital
val8 = read8(padapter, SYS_ISO_CTRL+1);
val8 = val8 & 0xEF;
write8(padapter, SYS_ISO_CTRL+1, val8);//attatch AFE PLL to MACTOP/BB/PCIe Digital
val8 = read8(padapter, AFE_XTAL_CTRL+1);
val8 = val8 & 0xFB;
write8(padapter, AFE_XTAL_CTRL+1, val8);//enable AFE clock
val8 = read8(padapter, AFE_PLL_CTRL);
val8 = val8 |0x01;
write8(padapter, AFE_PLL_CTRL, val8);//Enable AFE PLL Macro Block
val8 = 0xEE;
write8(padapter, SYS_ISO_CTRL, val8);//release isolation AFE PLL & MD
val8 = read8(padapter, SYS_CLKR+1);
val8 = val8 |0x08;
write8(padapter, SYS_CLKR+1, val8);//enable MAC clock
val8 = read8(padapter, SYS_FUNC_EN+1);
val8 = val8 |0x08;
write8(padapter, SYS_FUNC_EN+1, val8);//enable Core digital and enable IOREG R/W
val8 = val8 |0x80;
write8(padapter, SYS_FUNC_EN+1, val8);//enable REG_EN
val8 = read8(padapter, SYS_CLKR+1);
val8 = (val8 |0x80)&0xBF;
write8(padapter, SYS_CLKR + 1, val8);//switch the control path
val8 = 0xFC;
write8(padapter, CR, val8);
val8 = 0x37;
write8(padapter, CR+1, val8);
#define USE_SIX_USB_ENDPOINT
#ifdef USE_SIX_USB_ENDPOINT
//reduce EndPoint & init it
write8(padapter, 0x102500ab, read8(padapter, 0x102500ab)|BIT(6)|BIT(7));
#endif
//consideration of power consumption - init
write8(padapter, 0x10250008, read8(padapter, 0x10250008)&0xfffffffb);
}
else if(pregistrypriv->chip_version == RTL8712_1stCUT)
{
//Initialization for power on sequence, Revised by Roger. 2008.09.03.
//Revised POS, suggested by SD1 Alex, 2008.09.27.
write8(padapter, SPS0_CTRL+1, 0x53);
write8(padapter, SPS0_CTRL, 0x57);
//Enable AFE Macro Block's Bandgap adn Enable AFE Macro Block's Mbias
val8 = read8(padapter, AFE_MISC);
write8(padapter, AFE_MISC, (val8|AFE_MISC_BGEN|AFE_MISC_MBEN));
//Enable LDOA15 block
val8 = read8(padapter, LDOA15_CTRL);
write8(padapter, LDOA15_CTRL, (val8|LDA15_EN));
val8 = read8(padapter, SPS1_CTRL);
write8(padapter, SPS1_CTRL, (val8|SPS1_LDEN));
msleep_os(2);
//Enable Switch Regulator Block
val8 = read8(padapter, SPS1_CTRL);
write8(padapter, SPS1_CTRL, (val8|SPS1_SWEN));
write32(padapter, SPS1_CTRL, 0x00a7b267);//?
val8 = read8(padapter, SYS_ISO_CTRL+1);
write8(padapter, SYS_ISO_CTRL+1, (val8|0x08));
//Engineer Packet CP test Enable
val8 = read8(padapter, SYS_FUNC_EN+1);
write8(padapter, SYS_FUNC_EN+1, (val8|0x20));
val8 = read8(padapter, SYS_ISO_CTRL+1);
write8(padapter, SYS_ISO_CTRL+1, (val8& 0x6F));
//Enable AFE clock
val8 = read8(padapter, AFE_XTAL_CTRL+1);
write8(padapter, AFE_XTAL_CTRL+1, (val8& 0xfb));
//Enable AFE PLL Macro Block
val8 = read8(padapter, AFE_PLL_CTRL);
write8(padapter, AFE_PLL_CTRL, (val8|0x11));
//Attatch AFE PLL to MACTOP/BB/PCIe Digital
val8 = read8(padapter, SYS_ISO_CTRL);
write8(padapter, SYS_ISO_CTRL, (val8&0xEE));
// Switch to 40M clock
val8 = read8(padapter, SYS_CLKR);
write8(padapter, SYS_CLKR, val8 & (~ SYS_CLKSEL));
//SSC Disable
val8 = read8(padapter, SYS_CLKR);
//write8(padapter, SYS_CLKR, (val8&0x5f));
//Enable MAC clock
val8 = read8(padapter, SYS_CLKR+1);
write8(padapter, SYS_CLKR+1, (val8|0x18));
//Revised POS, suggested by SD1 Alex, 2008.09.27.
write8(padapter, PMC_FSM, 0x02);
//Enable Core digital and enable IOREG R/W
val8 = read8(padapter, SYS_FUNC_EN+1);
write8(padapter, SYS_FUNC_EN+1, (val8|0x08));
//Enable REG_EN
val8 = read8(padapter, SYS_FUNC_EN+1);
write8(padapter, SYS_FUNC_EN+1, (val8|0x80));
//Switch the control path to FW
val8 = read8(padapter, SYS_CLKR+1);
write8(padapter, SYS_CLKR+1, (val8|0x80)& 0xBF);
write8(padapter, CR, 0xFC);
write8(padapter, CR+1, 0x37);
//Fix the RX FIFO issue(usb error), 970410
val8 = read8(padapter, 0x1025FE5c);
write8(padapter, 0x1025FE5c, (val8|BIT(7)));
#define USE_SIX_USB_ENDPOINT
#ifdef USE_SIX_USB_ENDPOINT
val8 = read8(padapter, 0x102500ab);
write8(padapter, 0x102500ab, (val8|BIT(6)|BIT(7)));
#endif
//For power save, used this in the bit file after 970621
val8 = read8(padapter, SYS_CLKR);
write8(padapter, SYS_CLKR, val8&(~CPU_CLKSEL));
}
else if(pregistrypriv->chip_version == RTL8712_2ndCUT || pregistrypriv->chip_version == RTL8712_3rdCUT)
{
//Initialization for power on sequence, Revised by Roger. 2008.09.03.
//E-Fuse leakage prevention sequence
write8(padapter, 0x37, 0xb0);
msleep_os(10);
write8(padapter, 0x37, 0x30);
//
//<Roger_Notes> Set control path switch to HW control and reset Digital Core, CPU Core and
// MAC I/O to solve FW download fail when system from resume sate.
// 2008.11.04.
//
val8 = read8(padapter, SYS_CLKR+1);
//DbgPrint("SYS_CLKR+1=0x%x\n", val8);
if(val8 & 0x80)
{
val8 &= 0x3f;
write8(padapter, SYS_CLKR+1, val8);
}
val8 = read8(padapter, SYS_FUNC_EN+1);
//DbgPrint("SYS_FUNC_EN+1=0x%x\n", val8);
val8 &= 0x73;
write8(padapter, SYS_FUNC_EN+1, val8);
udelay_os(1000);
//msleep_os(100);//PlatformStallExecution(1000);
//Revised POS, suggested by SD1 Alex, 2008.09.27.
write8(padapter, SPS0_CTRL+1, 0x53);
write8(padapter, SPS0_CTRL, 0x57);// Switching 18V to PWM.
//DbgPrint("SPS0_CTRL+1=0x%x\n", read8(padapter, SPS0_CTRL+1));
//DbgPrint("SPS0_CTRL=0x%x\n", read8(padapter, SPS0_CTRL));
//Enable AFE Macro Block's Bandgap adn Enable AFE Macro Block's Mbias
val8 = read8(padapter, AFE_MISC);
//DbgPrint("AFE_MISC=0x%x\n", val8);
//write8(padapter, AFE_MISC, (val8|AFE_MISC_BGEN|AFE_MISC_MBEN));
write8(padapter, AFE_MISC, (val8|AFE_MISC_BGEN)); //Bandgap
write8(padapter, AFE_MISC, (val8|AFE_MISC_BGEN|AFE_MISC_MBEN | AFE_MISC_I32_EN)); //Mbios
//Enable LDOA15 block -> //Enable PLL Power (LDOA15V)
val8 = read8(padapter, LDOA15_CTRL);
//DbgPrint("LDOA15_CTRL=0x%x\n", val8);
write8(padapter, LDOA15_CTRL, (val8|LDA15_EN));
//val8 = read8(padapter, SPS1_CTRL);
//write8(padapter, SPS1_CTRL, (val8|SPS1_LDEN));
//msleep_os(2);
//Enable LDOV12D block
val8 = read8(padapter, LDOV12D_CTRL);
//DbgPrint("LDOV12D_CTRL=0x%x\n", val8);
write8(padapter, LDOV12D_CTRL, (val8|LDV12_EN));
//Enable Switch Regulator Block
//val8 = read8(padapter, SPS1_CTRL);
//write8(padapter, SPS1_CTRL, (val8|SPS1_SWEN));
//write32(padapter, SPS1_CTRL, 0x00a7b267);//?
val8 = read8(padapter, SYS_ISO_CTRL+1);
//DbgPrint("SYS_ISO_CTRL+1=0x%x\n", val8);
write8(padapter, SYS_ISO_CTRL+1, (val8|0x08));
//Engineer Packet CP test Enable
val8 = read8(padapter, SYS_FUNC_EN+1);
//DbgPrint("SYS_FUNC_EN+1=0x%x\n", val8);
write8(padapter, SYS_FUNC_EN+1, (val8|0x20));
//Support 64k IMEM, suggested by SD1 Alex.
val8 = read8(padapter, SYS_ISO_CTRL+1);
//DbgPrint("SYS_ISO_CTRL+1=0x%x\n", val8);
//write8(padapter, SYS_ISO_CTRL+1, (val8& 0x6F));
write8(padapter, SYS_ISO_CTRL+1, (val8&0x68));
//Enable AFE clock
val8 = read8(padapter, AFE_XTAL_CTRL+1);
//DbgPrint("AFE_XTAL_CTRL+1=0x%x\n", val8);
write8(padapter, AFE_XTAL_CTRL+1, (val8& 0xfb));
//Enable AFE PLL Macro Block
val8 = read8(padapter, AFE_PLL_CTRL);
//DbgPrint("AFE_PLL_CTRL=0x%x\n", val8);
write8(padapter, AFE_PLL_CTRL, (val8|0x11));
//(20090928) for some sample will download fw failure
udelay_os(1000);
write8(padapter, AFE_PLL_CTRL, (val8|0x51));
udelay_os(100);
write8(padapter, AFE_PLL_CTRL, (val8|0x11));
udelay_os(100);
//Attatch AFE PLL to MACTOP/BB/PCIe Digital
val8 = read8(padapter, SYS_ISO_CTRL);
//DbgPrint("SYS_ISO_CTRL=0x%x\n", val8);
write8(padapter, SYS_ISO_CTRL, (val8&0xEE));
// Switch to 40M clock
write8(padapter, SYS_CLKR, 0x00);
//CPU Clock and 80M Clock SSC Disable to overcome FW download fail timing issue.
val8 = read8(padapter, SYS_CLKR);
write8(padapter, SYS_CLKR, (val8|0xa0));
//Enable MAC clock
val8 = read8(padapter, SYS_CLKR+1);
//DbgPrint("SYS_CLKR+1=0x%x\n", val8);
write8(padapter, SYS_CLKR+1, (val8|0x18));
//Revised POS, suggested by SD1 Alex, 2008.09.27.
write8(padapter, PMC_FSM, 0x02);
//DbgPrint("PMC_FSM=0x%x\n", read8(padapter, PMC_FSM));
//Enable Core digital and enable IOREG R/W
val8 = read8(padapter, SYS_FUNC_EN+1);
//DbgPrint("SYS_FUNC_EN+1=0x%x\n", val8);
write8(padapter, SYS_FUNC_EN+1, (val8|0x08));
//Enable REG_EN
val8 = read8(padapter, SYS_FUNC_EN+1);
//DbgPrint("SYS_FUNC_EN+1=0x%x\n", val8);
write8(padapter, SYS_FUNC_EN+1, (val8|0x80));
//Switch the control path to FW
val8 = read8(padapter, SYS_CLKR+1);
//DbgPrint("SYS_CLKR+1=0x%x\n", val8);
write8(padapter, SYS_CLKR+1, (val8|0x80)& 0xBF);
write8(padapter, CR, 0xFC);
write8(padapter, CR+1, 0x37);
//Fix the RX FIFO issue(usb error), 970410
val8 = read8(padapter, 0x1025FE5c);
//DbgPrint("0x1025FE5c=0x%x\n", val8);
write8(padapter, 0x1025FE5c, (val8|BIT(7)));
#if 0 //fw will help set it depending on the fwpriv.
#define USE_SIX_USB_ENDPOINT
#ifdef USE_SIX_USB_ENDPOINT
val8 = read8(padapter, 0x102500ab);
write8(padapter, 0x102500ab, (val8|BIT(6)|BIT(7)));
#endif
#endif
//For power save, used this in the bit file after 970621
val8 = read8(padapter, SYS_CLKR);
write8(padapter, SYS_CLKR, val8&(~CPU_CLKSEL));
//DbgPrint("SYS_CLKR=0x%x\n", read8(padapter, SYS_CLKR));
// Revised for 8051 ROM code wrong operation. Added by Roger. 2008.10.16.
write8(padapter, 0x1025fe1c, 0x80);
//
// <Roger_EXP> To make sure that TxDMA can ready to download FW.
// We should reset TxDMA if IMEM RPT was not ready.
// Suggested by SD1 Alex. 2008.10.23.
//
do
{
val8 = read8(padapter, TCR);
if((val8 & _TXDMA_INIT_VALUE) == _TXDMA_INIT_VALUE)
break;
udelay_os(5);//PlatformStallExecution(5);
}while(PollingCnt--); // Delay 1ms
if(PollingCnt <= 0 )
{
//ERR_8712("MacConfigBeforeFwDownloadASIC(): Polling _TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", val8);
val8 = read8(padapter, CR);
write8(padapter, CR, val8&(~_TXDMA_EN));
udelay_os(2);//PlatformStallExecution(2);
write8(padapter, CR, val8|_TXDMA_EN);// Reset TxDMA
}
}
else
{
ret = _FAIL;
}
return ret;
}
