SLOT_INTERFACE_END
WRITE_LINE_MEMBER( bullet_state::fdc_drq_w )
{
m_fdrdy = !state;
update_dma_rdy();
}
void bullet_state::machine_reset()
{
// memory banking
m_brom = 0;
m_segst = 0;
// DMA ready
m_exdma = 0;
m_buf = 0;
update_dma_rdy();
}
void bulletf_state::machine_reset()
{
// memory banking
m_rome = 0;
m_mbank = 0;
// DMA ready
m_xdma0 = 0;
m_wack = 0;
m_wrdy = 0;
update_dma_rdy();
}
void bullet_state::machine_reset()
{
// memory banking
m_brom = 0;
m_segst = 0;
// DMA ready
m_exdma = 0;
m_buf = 0;
update_dma_rdy();
// disable software control
m_exdsk_sw = false;
m_hdcon_sw = false;
uint8_t sw1 = m_sw1->read();
int mini = BIT(sw1, 6);
m_fdc->set_unscaled_clock(mini ? XTAL_16MHz/16 : XTAL_16MHz/8);
m_fdc->dden_w(BIT(sw1, 7));
if (mini)
{
m_floppy = m_floppy0->get_device();
}
else
{
m_floppy = m_floppy4->get_device();
}
m_fdc->set_floppy(m_floppy);
if (m_floppy)
{
m_floppy->ss_w(0);
m_floppy->mon_w(0);
}
}
void bullet_state::fdc_drq_w(bool state)
{
m_fdrdy = !state;
update_dma_rdy();
}
