void pc1512_state::set_fdc_dsr(UINT8 data)
{
/*
bit description
0 Drive Select Bit 0 (DS0)
1 Drive Select Bit 1 (DS1)
2 765A reset
3 Allow 765A FDC to interrupt and request DMA
4 Switch motor(s) on and enable drive 0 selection
5 Switch motor(s) on and enable drive 1 selection
6
7
*/
m_fdc_dsr = data;
m_nden = BIT(data, 3);
update_fdc_int();
update_fdc_drq();
update_fdc_tc();
upd765_reset_w(m_fdc, BIT(data, 2));
floppy_mon_w(m_floppy0, BIT(data, 4) ? CLEAR_LINE : ASSERT_LINE);
floppy_mon_w(m_floppy1, BIT(data, 5) ? CLEAR_LINE : ASSERT_LINE);
}
void pc1512_state::fdc_int_w(bool state)
{
m_dint = state;
update_fdc_int();
}
INPUT_PORTS_END
//**************************************************************************
// DEVICE CONFIGURATION
//**************************************************************************
//-------------------------------------------------
// I8255A INTERFACE( ppi0_intf )
//-------------------------------------------------
/*
IR0 U74 OUT2
IR1 RX2I+
IR2 TX1I+
IR3 TX2I+
IR4 MI-
IR5 CNI+
IR6 U74 OUT0
IR7 SI+
*/
//-------------------------------------------------
// I8255A INTERFACE( ppi0_intf )
//-------------------------------------------------
WRITE8_MEMBER( sage2_state::ppi0_pc_w )
{
/*
bit signal
PC0 TC+
PC1 RDY+
PC2 FDIE+
PC3 SL0-
PC4 SL1-
PC5 MOT-
PC6 PCRMP-
PC7 FRES+
*/
// floppy terminal count
m_fdc->tc_w(BIT(data, 0));
// floppy ready
m_fdc->ready_w(BIT(data, 1));
// floppy interrupt enable
m_fdie = BIT(data, 2);
update_fdc_int();
// drive select
m_floppy = nullptr;
if (!BIT(data, 3)) m_floppy = m_floppy0->get_device();
if (!BIT(data, 4)) m_floppy = m_floppy1->get_device();
m_fdc->set_floppy(m_floppy);
// floppy motor
if (m_floppy) m_floppy->mon_w(BIT(data, 5));
// FDC reset
if(BIT(data, 7)) m_fdc->reset();
}
void sage2_state::fdc_irq(bool state)
{
m_fdc_int = state;
update_fdc_int();
}
