static void
uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
SiFiveUARTState *s = opaque;
uint32_t value = val64;
unsigned char ch = value;
switch (addr) {
case SIFIVE_UART_TXFIFO:
qemu_chr_fe_write(&s->chr, &ch, 1);
update_irq(s);
return;
case SIFIVE_UART_IE:
s->ie = val64;
update_irq(s);
return;
case SIFIVE_UART_TXCTRL:
s->txctrl = val64;
return;
case SIFIVE_UART_RXCTRL:
s->rxctrl = val64;
return;
case SIFIVE_UART_DIV:
s->div = val64;
return;
}
hw_error("%s: bad write: addr=0x%x v=0x%x\n",
__func__, (int)addr, (int)value);
}
void pfifo_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
{
NV2AState *d = (NV2AState *)opaque;
reg_log_write(NV_PFIFO, addr, val);
qemu_mutex_lock(&d->pfifo.lock);
switch (addr) {
case NV_PFIFO_INTR_0:
d->pfifo.pending_interrupts &= ~val;
update_irq(d);
break;
case NV_PFIFO_INTR_EN_0:
d->pfifo.enabled_interrupts = val;
update_irq(d);
break;
default:
d->pfifo.regs[addr] = val;
break;
}
qemu_cond_broadcast(&d->pfifo.pusher_cond);
qemu_cond_broadcast(&d->pfifo.puller_cond);
qemu_mutex_unlock(&d->pfifo.lock);
}
void mos6530_base_t::timer_w(offs_t offset, UINT8 data, bool ie)
{
live_sync();
m_timer = data;
switch (offset & 0x03) {
case 0: m_prescale = 1; break;
case 1: m_prescale = 8; break;
case 2: m_prescale = 64; break;
case 3: m_prescale = 1024; break;
}
m_ie_timer = ie;
if (cur_live.tm_irq != machine().time()) {
m_irq_timer = false;
}
update_irq();
if (LOG_TIMER) logerror("%s %s %s '%s' Timer value %02x prescale %u IE %u\n", machine().time().as_string(), machine().describe_context(), name(), tag(), data, m_prescale, m_ie_timer ? 1 : 0);
checkpoint();
if (cur_live.state != IDLE) {
live_abort();
}
live_start();
live_run();
}
static INTERRUPT_GEN( vblank_interrupt )
{
othunder_state *state = device->machine().driver_data<othunder_state>();
state->m_vblank_irq = 1;
update_irq(device->machine());
}
static TIMER_CALLBACK( ad_interrupt )
{
othunder_state *state = machine.driver_data<othunder_state>();
state->m_ad_irq = 1;
update_irq(machine);
}
bool wd33c9x_base_device::set_command_length(const uint8_t cc)
{
const bool eaf = ((m_regs[OWN_ID] & OWN_ID_EAF) != 0);
bool ret;
if (eaf && (cc == COMMAND_CC_SELECT_TRANSFER || cc == COMMAND_CC_SELECT_ATN_TRANSFER)) {
m_command_length &= OWN_ID_CDB_SIZE;
ret = true;
}
else if (eaf && cc == COMMAND_CC_WAIT_SELECT_RECEIVE_DATA) {
m_command_length = 6;
m_regs[COMMAND_PHASE] = COMMAND_PHASE_CP_BYTES_1;
irq_fifo_push(SCSI_STATUS_NEED_COMMAND_SIZE);
update_irq();
ret = false;
}
else {
switch (m_regs[CDB_1] >> 5) {
default:
case 0: m_command_length = 6; break;
case 1: m_command_length = 10; break;
case 5: m_command_length = 12; break;
}
ret = true;
}
LOGMASKED(LOG_COMMANDS, "%s: SCSI Command Length %d bytes\n", shortname(), m_command_length);
return ret;
}
static void
pic_write(void *opaque, target_phys_addr_t addr,
uint64_t val64, unsigned int size)
{
struct xlx_pic *p = opaque;
uint32_t value = val64;
addr >>= 2;
D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
switch (addr)
{
case R_IAR:
p->regs[R_ISR] &= ~value; /* ACK. */
break;
case R_SIE:
p->regs[R_IER] |= value; /* Atomic set ie. */
break;
case R_CIE:
p->regs[R_IER] &= ~value; /* Atomic clear ie. */
break;
default:
if (addr < ARRAY_SIZE(p->regs))
p->regs[addr] = value;
break;
}
update_irq(p);
}
void mos6530_base_t::device_reset()
{
m_pa_out = 0;
m_pa_ddr = 0;
m_pb_out = 0;
m_pb_ddr = 0;
m_ie_timer = false;
m_irq_timer = false;
m_ie_edge = false;
m_irq_edge = false;
m_pa7_dir = 0;
update_pa();
update_pb();
update_irq();
edge_detect();
m_timer = 0xff;
m_prescale = 1024;
if (cur_live.state != IDLE) {
live_abort();
}
live_start();
live_run();
}
void mc146818_device::nvram_default()
{
// populate from a memory region if present
if (m_region != NULL)
{
UINT32 bytes = m_region->bytes();
if (bytes > data_size())
bytes = data_size();
memcpy(&m_data[0], m_region->base(), bytes);
}
else
{
memset(&m_data[0], 0, data_size());
}
if(m_binary)
m_data[REG_B] |= REG_B_DM;
if(m_hour)
m_data[REG_B] |= REG_B_24_12;
set_base_datetime();
update_timer();
update_irq();
}
static uint64_t
uart_read(void *opaque, hwaddr addr, unsigned int size)
{
SiFiveUARTState *s = opaque;
unsigned char r;
switch (addr) {
case SIFIVE_UART_RXFIFO:
if (s->rx_fifo_len) {
r = s->rx_fifo[0];
memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);
s->rx_fifo_len--;
qemu_chr_fe_accept_input(&s->chr);
update_irq(s);
return r;
}
return 0x80000000;
case SIFIVE_UART_TXFIFO:
return 0; /* Should check tx fifo */
case SIFIVE_UART_IE:
return s->ie;
case SIFIVE_UART_IP:
return uart_ip(s);
case SIFIVE_UART_TXCTRL:
return s->txctrl;
case SIFIVE_UART_RXCTRL:
return s->rxctrl;
case SIFIVE_UART_DIV:
return s->div;
}
hw_error("%s: bad read: addr=0x%x\n",
__func__, (int)addr);
return 0;
}
void mc146818_device::device_reset()
{
m_data[REG_B] &= ~(REG_B_UIE | REG_B_AIE | REG_B_PIE | REG_B_SQWE);
m_data[REG_C] = 0;
update_irq();
}
void mos6530_base_t::device_reset()
{
m_pa_out = 0xff;
m_pa_ddr = 0;
m_pb_out = 0xff; // a7800 One-On-One Basketball (1on1u) needs this or you can't start a game, it doesn't initialize it. (see MT6060)
m_pb_ddr = 0;
m_ie_timer = false;
m_irq_timer = false;
m_ie_edge = false;
m_irq_edge = false;
m_pa7_dir = 0;
update_pa();
update_pb();
update_irq();
edge_detect();
m_timer = 0xff;
m_prescale = 1024;
if (cur_live.state != IDLE) {
live_abort();
}
live_start();
live_run();
}
void Cm6502::run_one_opecode()
{
// if an irq is pending, take it now
if(nmi_state) {
EAD = NMI_VEC;
CYCLES(2);
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
P |= F_I; // set I flag
PCL = RDMEM(EAD);
PCH = RDMEM(EAD + 1);
CallSubLevel++;
nmi_state = false;
halt=false;
AddLog(LOG_CONSOLE,"CPU RUNNING\n");
// qWarning()<<"CPU RUNNING";
if (fp_log) fprintf(fp_log,"\n INT NMI newpc:%04x\n",PCW);
}
else if(pending_irq) {
if (halt) Reset();
else update_irq();
}
if (halt) {
CYCLES(50);
P &= ~F_I;
return;
}
prev_pc = pc.w.l;
quint8 code = RDOP();
OP(code);
// check if the I flag was just reset (interrupts enabled)
if(after_cli) {
after_cli = false;
if(irq_state) {
if (fp_log) fprintf(fp_log,"\n INT after_cli irq\n");
pending_irq = true;
}
}
else if(pending_irq) {
update_irq();
}
}
/* This routine must be called when CR_IENABLE is modified */
void nios2_iic_update_cr_ienable(DeviceState *d)
{
/* Modify the IPENDING register */
AlteraIIC *s = ALTERA_IIC(d);
CPUNios2State *env = &s->cpu->env;
env->regs[CR_IPENDING] = env->regs[CR_IENABLE] & s->irqs;
update_irq(s);
}
void mc146818_device::nvram_read(emu_file &file)
{
file.read(m_data, data_size());
set_base_datetime();
update_timer();
update_irq();
}
void mos6530_base_t::live_run(const attotime &limit)
{
if(cur_live.state == IDLE || cur_live.next_state != -1)
return;
for(;;) {
switch(cur_live.state) {
case RUNNING: {
if (cur_live.tm > limit)
return;
cur_live.value--;
if (cur_live.value == 0xff) {
live_delay(RUNNING_SYNCPOINT);
return;
} else {
if (LOG_TIMER) logerror("%s %s '%s' timer %02x\n", cur_live.tm.as_string(), name(), tag(), cur_live.value);
cur_live.tm += cur_live.period;
}
break;
}
case RUNNING_SYNCPOINT: {
if (LOG_TIMER) logerror("%s %s '%s' timer %02x interrupt\n", cur_live.tm.as_string(), name(), tag(), cur_live.value);
cur_live.tm_irq = cur_live.tm;
m_irq_timer = true;
update_irq();
checkpoint();
cur_live.state = RUNNING_AFTER_INTERRUPT;
cur_live.period = attotime::from_hz(clock());
cur_live.tm += cur_live.period;
break;
}
case RUNNING_AFTER_INTERRUPT: {
if (cur_live.tm > limit)
return;
cur_live.value--;
if (LOG_TIMER) logerror("%s %s '%s' timer %02x\n", cur_live.tm.as_string(), name(), tag(), cur_live.value);
if (!cur_live.value) {
cur_live.state = IDLE;
return;
}
cur_live.tm += cur_live.period;
break;
}
}
}
}
void lm32_pic_set_im(DeviceState *d, uint32_t im)
{
LM32PicState *s = container_of(d, LM32PicState, busdev.qdev);
trace_lm32_pic_set_im(im);
s->im = im;
update_irq(s);
}
void hp98x5_io_sys_device::set_irq(uint8_t sc , int state)
{
if (state) {
BIT_SET(m_irq_pending, sc);
} else {
BIT_CLR(m_irq_pending, sc);
}
update_irq();
}
void lm32_pic_set_im(DeviceState *d, uint32_t im)
{
LM32PicState *s = LM32_PIC(d);
trace_lm32_pic_set_im(im);
s->im = im;
update_irq(s);
}
static void riotcore_int_riot(CLOCK offset, void *data)
{
riot_context_t *riot_context = (riot_context_t *)data;
/* CLOCK rclk = *(riot_context->clk_ptr) - offset; */
alarm_unset(riot_context->alarm);
update_irq(riot_context, (BYTE)(riot_context->r_irqfl | 0x80));
}
static void irq_handler(void *opaque, int irq, int level)
{
AlteraIIC *pv = opaque;
CPUNios2State *env = &((Nios2CPU*)(pv->cpu))->env;
env->regs[CR_IPENDING] &= ~(1 << irq);
env->regs[CR_IPENDING] |= level << irq;
update_irq(pv);
}
/* Emulate the CR_IPENDING register */
static void irq_handler(void *opaque, int irq, int level)
{
AlteraIIC *s = opaque;
CPUNios2State *env = &s->cpu->env;
/* Keep track of IRQ lines states */
s->irqs &= ~(1 << irq);
s->irqs |= level << irq;
env->regs[CR_IPENDING] = env->regs[CR_IENABLE] & s->irqs;
update_irq(s);
}
void lm32_pic_set_ip(DeviceState *d, uint32_t ip)
{
LM32PicState *s = container_of(d, LM32PicState, busdev.qdev);
trace_lm32_pic_set_ip(ip);
/* ack interrupt */
s->ip &= ~ip;
update_irq(s);
}
void hp98x5_io_sys_device::device_reset()
{
m_irq_pending = 0;
update_irq();
m_pa = 0;
m_flg_status = 0;
m_sts_status = 0;
update_flg_sts();
m_dmar_status = 0;
update_dmar();
}
void lm32_pic_set_ip(DeviceState *d, uint32_t ip)
{
LM32PicState *s = LM32_PIC(d);
trace_lm32_pic_set_ip(ip);
/* ack interrupt */
s->ip &= ~ip;
update_irq(s);
}
void othunder_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
switch (id)
{
case TIMER_AD_INTERRUPT:
m_ad_irq = 1;
update_irq();
break;
default:
assert_always(FALSE, "Unknown id in othunder_state::device_timer");
}
}
static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
SiFiveUARTState *s = opaque;
/* Got a byte. */
if (s->rx_fifo_len >= sizeof(s->rx_fifo)) {
printf("WARNING: UART dropped char.\n");
return;
}
s->rx_fifo[s->rx_fifo_len++] = *buf;
update_irq(s);
}
static void irq_handler(void *opaque, int irq, int level)
{
struct xlx_pic *p = opaque;
/* edge triggered interrupt */
if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
p->regs[R_ISR] |= (level << irq);
}
p->irq_pin_state &= ~(1 << irq);
p->irq_pin_state |= level << irq;
update_irq(p);
}
void hp98035_io_card::half_init(void)
{
m_inten = false;
m_intflag = false;
m_irq = false;
update_irq();
m_np_irq = false;
update_dc();
m_clock_1s_div = 0;
m_clock_state = CLOCK_OFF;
m_clock_mux = 0;
regen_clock_image();
}
static WRITE16_HANDLER( irq_ack_w )
{
switch (offset)
{
case 0:
vblank_irq = 0;
break;
case 1:
ad_irq = 0;
break;
}
update_irq();
}
