void slp_pmic_init(void)
{
/* VPROC = 0.9V in sleep mode */
upmu_buck_vosel_srclken_0(BUCK_VPROC, 0x08);
upmu_buck_ctrl(BUCK_VPROC, 0x3);
/* VCORE = 0.9V in sleep mode */
upmu_buck_vosel(BUCK_VCORE, UPMU_VOLT_0_9_0_0_V);
/* VM12_INT = 0.9V in sleep mode */
pmic_config_interface(0x8b, 0x08, 0x1f, 0x0);
pmic_config_interface(0x8f, 0x1, 0x1, 0x4);
}
void mt_pmic_low_power_init(void)
{
unsigned int volt = 0;
/********************
* PMIC VPROC setting
*********************/
upmu_buck_vosel_srclken_0(BUCK_VPROC, 0x08); // VPROC 0.9V in sleep mode
if (get_chip_ver() >= CHIP_6577_E1)
{
volt = mt_pmic_cpu_max_volt();
if ((DRV_Reg32(HW_RESV) & (0x1 << 23)) && ((DRV_Reg32(HW_RESV) & (0x1 << 20)) == 0))
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, volt);
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17); // 1.275V DVS_VOL_11
}
else
{
if (DRV_Reg32(HW_RESV) & (0x1 << 12))
{
if ((DRV_Reg32(HW_RESV) & (0x1 << 17)) && ((DRV_Reg32(HW_RESV) & (0x1 << 16)) == 0))
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, volt);
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17); // 1.275V DVS_VOL_11
}
else
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x08); // 0.900V DVS_VOL_00
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10
upmu_buck_vosel_dvs_11(BUCK_VPROC, volt);
}
}
else
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x08); // 0.900V DVS_VOL_00
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10
upmu_buck_vosel_dvs_11(BUCK_VPROC, volt);
}
}
}
else if (get_chip_ver() >= CHIP_6575_E2)
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x0B);
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F);
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13);
if ((DRV_Reg32(HW_RESV) & (0x1 << 29)))
{
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17);
}
else
{
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x16);
}
}
else if (get_chip_ver() >= CHIP_6575_E1)
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x13);
if ((DRV_Reg32(HW_RESV) & (0x1 << 29)))
{
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x17);
}
else
{
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x16);
}
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13);
if ((DRV_Reg32(HW_RESV) & (0x1 << 29)))
{
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17);
}
else
{
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x16);
}
}
else
{
upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x16);
upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x16);
upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x16);
upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x16);
}
DRV_WriteReg32(SC_AP_DVFS_CON, ((DRV_Reg32(SC_AP_DVFS_CON) & 0xFFFFFFFC) | 0x03)); // set cpu to top voltage
upmu_buck_ctrl(BUCK_VPROC, 0x3); // VPROC controlled by SRCLKEN and AP_DVFS_CON1/0
/********************
* PMIC VCORE setting
*********************/
if ((DRV_Reg32(HW_RESV) & (0x1 << 19)))
{
upmu_buck_vosel(BUCK_VCORE, UPMU_VOLT_0_8_0_0_V); // VCORE 0.8V in sleep mode
}
else
{
upmu_buck_vosel(BUCK_VCORE, UPMU_VOLT_0_9_0_0_V); // VCORE 0.9V in sleep mode
}
/********************
* PMIC Other setting
*********************/
pmic_config_interface(0x8B, 0x08, 0x1F, 0x0); // VM12_INT 0.9V in sleep mode
pmic_config_interface(0x8C, 0x10, 0x1F, 0x0); // VM12_INT_LOW_BOUND
pmic_config_interface(0x8F, 0x01, 0x01, 0x4); // VM12_INT Tracking VPROC
pmic_config_interface(0x90, 0x01, 0x01, 0x0); // VM12_INT_LP_SEL HW control
pmic_config_interface(0x85, 0x01, 0x01, 0x0); // VM12_1_LP_SEL HW control
pmic_config_interface(0x89, 0x01, 0x01, 0x0); // VM12_2_LP_SEL HW control
pmic_config_interface(0xA9, 0x01, 0x01, 0x0); // VMC_LP_SEL HW control
pmic_config_interface(0xAD, 0x01, 0x01, 0x0); // VMCH_LP_SEL HW control
pmic_config_interface(0xC6, 0x01, 0x01, 0x0); // VA1_LP_SEL HW control
pmic_config_interface(0xC1, 0x01, 0x01, 0x1); // VTCXO_ON_CTRL HW control
pmic_config_interface(0x4F, 0x01, 0x01, 0x6); // BUCK clock keep 2MHz select
pmic_config_interface(0x4F, 0x01, 0x01, 0x7); // OSC10M and 2M auto select function enable
}