//==============================================================================
// PMIC-AUXADC related API
//==============================================================================
void pmic_auxadc_init(void)
{
kal_int32 adc_busy;
wake_lock_init(&pmicAuxadc_irq_lock, WAKE_LOCK_SUSPEND, "pmicAuxadc irq wakelock");
mt6325_upmu_set_rg_vref18_enb(0);
mutex_lock(&pmic_adc_mutex);
//change to suspend/resume
pmic_read_interface_nolock(MT6325_AUXADC_ADC19, &adc_busy, MT6325_PMIC_RG_ADC_BUSY_MASK, MT6325_PMIC_RG_ADC_BUSY_SHIFT);
if (adc_busy==0) {
pmic_config_interface_nolock(MT6325_AUXADC_CON19, 0x0, MT6325_PMIC_RG_ADC_DECI_GDLY_MASK, MT6325_PMIC_RG_ADC_DECI_GDLY_SHIFT);
}
mutex_unlock(&pmic_adc_mutex);
mt6325_upmu_set_rg_adc_gps_status(1);
mt6325_upmu_set_rg_adc_md_status(1);
mt6325_upmu_set_rg_deci_gdly_vref18_selb(1);
mt6325_upmu_set_rg_deci_gdly_sel_mode(1);
//*set CLK as 26MHz CLK
mt6325_upmu_set_rg_auxadc_ck_cksel(1);
//1. set AUXADC CLK HW control
mt6325_upmu_set_rg_auxadc_ck_pdn_hwen(1);
//2. turn on AP & MD
mt6325_upmu_set_rg_clksq_en_aux_ap(1);
mt6325_upmu_set_auxadc_ck_aon(1);
mt6325_upmu_set_strup_auxadc_rstb_sw(1);
mt6325_upmu_set_strup_auxadc_rstb_sel(1);
upmu_set_reg_value(0x0a08,0x010b);
upmu_set_reg_value(0x0f00,0x0005);
xlog_printk(ANDROID_LOG_INFO, "Power/PMIC", "****[pmic_auxadc_init] DONE\n");
}
//==============================================================================
// PMIC-AUXADC
//==============================================================================
kal_uint32 PMIC_IMM_GetOneChannelValue(mt6328_adc_ch_list_enum dwChannel, int deCount, int trimd)
{
kal_int32 ret=0;
kal_int32 ret_data;
kal_int32 r_val_temp=0;
kal_int32 adc_result=0;
int count;
kal_uint32 busy;
/*
CH0: BATSNS
CH1: ISENSE
CH2: VCDT
CH3: BAT ON
CH4: PMIC TEMP
CH5: ACCDET
CH6:
CH7: TSX
CH8:
CH9:
CH10:
CH11:
CH12:
CH13:
CH14:
CH15:
BATSNS 3v-4.5v
ISENSE 1.5-4.5v
BATON 0-1.8v
VCDT 4v-14v
ACCDET 1.8v
GPS 1.8v
*/
if(dwChannel>15)
return -1;
upmu_set_reg_value(0x0a44,0x010a);
upmu_set_reg_value(0x0cec,0x0000);
upmu_set_reg_value(0x0d00,0x0010);
upmu_set_reg_value(0x0f14,0x1290);
wake_lock(&pmicAuxadc_irq_lock);
mutex_lock(&pmic_adc_mutex);
//ret=pmic_config_interface(MT6328_TOP_CLKSQ_SET,(1<<2),0xffff,0);
ret=pmic_config_interface(MT6328_AUXADC_RQST0_SET,(1<<dwChannel),0xffff,0);
mutex_unlock(&pmic_adc_mutex);
busy=upmu_get_reg_value(0E84);
udelay(50);
switch(dwChannel){
case 0:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH0_BY_AP) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH0_BY_AP);
break;
case 1:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH1_BY_AP) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH1_BY_AP);
break;
case 2:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH2) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH2);
break;
case 3:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH3) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH3);
break;
case 4:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH4) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH4);
break;
case 5:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH5) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH5);
break;
case 6:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH6) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH6);
break;
case 7:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH7_BY_AP) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH7_BY_AP);
break;
case 8:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH8) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH8);
break;
case 9:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH9) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH9);
break;
case 10:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH10) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH10);
break;
case 11:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH11) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH11);
break;
case 12:
case 13:
case 14:
case 15:
while(mt6328_get_register_value(PMIC_AUXADC_ADC_RDY_CH12_15) != 1 )
{
msleep(1);
if( (count++) > count_time_out)
{
PMICLOG("[IMM_GetOneChannelValue_PMIC] (%d) Time out!\n", dwChannel);
break;
}
}
ret_data = mt6328_get_register_value(PMIC_AUXADC_ADC_OUT_CH12_15);
break;
default:
PMICLOG("[AUXADC] Invalid channel value(%d,%d)\n", dwChannel, trimd);
wake_unlock(&pmicAuxadc_irq_lock);
return -1;
break;
}
switch(dwChannel){
case 0:
r_val_temp = 3;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/32768;
break;
case 1:
r_val_temp = 3;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/32768;
break;
case 2:
r_val_temp = 1;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/4096;
break;
case 3:
r_val_temp = 1;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/4096;
break;
case 4:
r_val_temp = 1;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/4096;
break;
case 5:
r_val_temp = 1;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/4096;
break;
case 6:
r_val_temp = 1;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/4096;
break;
case 7:
r_val_temp = 1;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/32768;
break;
case 8:
r_val_temp = 1;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/4096;
break;
case 9:
case 10:
case 11:
case 12:
case 13:
case 14:
case 15:
case 16:
r_val_temp = 1;
adc_result = (ret_data*r_val_temp*VOLTAGE_FULL_RANGE)/4096;
break;
default:
PMICLOG("[AUXADC] Invalid channel value(%d,%d)\n", dwChannel, trimd);
wake_unlock(&pmicAuxadc_irq_lock);
return -1;
break;
}
wake_unlock(&pmicAuxadc_irq_lock);
PMICLOG("[AUXADC] ch=%d raw=%d data=%d \n", dwChannel, ret_data,adc_result);
return ret_data;
//return adc_result;
}
