int __init mx31_clocks_init(unsigned long fref) { u32 reg; ckih_rate = fref; clkdev_add_table(lookups, ARRAY_SIZE(lookups)); /* change the csi_clk parent if necessary */ reg = __raw_readl(MXC_CCM_CCMR); if (!(reg & MXC_CCM_CCMR_CSCS)) if (clk_set_parent(&csi_clk, &usb_pll_clk)) pr_err("%s: error changing csi_clk parent\n", __func__); /* Turn off all possible clocks */ __raw_writel((3 << 4), MXC_CCM_CGR0); __raw_writel(0, MXC_CCM_CGR1); __raw_writel((3 << 8) | (3 << 14) | (3 << 16)| 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for MX32, but still required to be set */ MXC_CCM_CGR2); /* * Before turning off usb_pll make sure ipg_per_clk is generated * by ipg_clk and not usb_pll. */ __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR); usb_pll_disable(&usb_pll_clk); pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); clk_enable(&gpt_clk); clk_enable(&emi_clk); clk_enable(&iim_clk); clk_enable(&serial_pll_clk); mx31_read_cpu_rev(); if (mx31_revision() >= MX31_CHIP_REV_2_0) { reg = __raw_readl(MXC_CCM_PMCR1); /* No PLL restart on DVFS switch; enable auto EMI handshake */ reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; __raw_writel(reg, MXC_CCM_PMCR1); } mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); return 0; }
int __init mx31_clocks_init(unsigned long fref) { u32 reg; ckih_rate = fref; clkdev_add_table(lookups, ARRAY_SIZE(lookups)); /* */ reg = __raw_readl(MXC_CCM_CCMR); if (!(reg & MXC_CCM_CCMR_CSCS)) if (clk_set_parent(&csi_clk, &usb_pll_clk)) pr_err("%s: error changing csi_clk parent\n", __func__); /* */ __raw_writel((3 << 4), MXC_CCM_CGR0); __raw_writel(0, MXC_CCM_CGR1); __raw_writel((3 << 8) | (3 << 14) | (3 << 16)| 1 << 27 | 1 << 28, /* */ MXC_CCM_CGR2); /* */ __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR); usb_pll_disable(&usb_pll_clk); pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); clk_enable(&gpt_clk); clk_enable(&emi_clk); clk_enable(&iim_clk); mx31_revision(); clk_disable(&iim_clk); clk_enable(&serial_pll_clk); if (mx31_revision() >= IMX_CHIP_REVISION_2_0) { reg = __raw_readl(MXC_CCM_PMCR1); /* */ reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; __raw_writel(reg, MXC_CCM_PMCR1); } mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); return 0; }
int __init mx31_clocks_init(unsigned long fref) { u32 reg; int i; mxc_set_cpu_type(MXC_CPU_MX31); ckih_rate = fref; for (i = 0; i < ARRAY_SIZE(lookups); i++) clkdev_add(&lookups[i]); /* Turn off all possible clocks */ __raw_writel((3 << 4), MXC_CCM_CGR0); __raw_writel(0, MXC_CCM_CGR1); __raw_writel((3 << 8) | (3 << 14) | (3 << 16)| 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for MX32, but still required to be set */ MXC_CCM_CGR2); usb_pll_disable(&usb_pll_clk); pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); clk_enable(&gpt_clk); clk_enable(&emi_clk); clk_enable(&iim_clk); clk_enable(&serial_pll_clk); if (mx31_revision() >= CHIP_REV_2_0) { reg = __raw_readl(MXC_CCM_PMCR1); /* No PLL restart on DVFS switch; enable auto EMI handshake */ reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; __raw_writel(reg, MXC_CCM_PMCR1); } mxc_timer_init(&ipg_clk); return 0; }