void up_irqinitialize(void)
{
int reg;
/* Disable all interrupts. We do this by writing ones to the IntClearEnable
* register.
*/
vic_putreg(0xffffffff, VIC_INTENCLEAR_OFFSET);
/* Select all IRQs, FIQs are not used */
vic_putreg(0, VIC_INTSELECT_OFFSET);
/* Clear priority interrupts */
for (reg = 0; reg < NR_IRQS; reg++)
{
vic_putreg(0, VIC_VECTADDR0_OFFSET + (reg << 2));
vic_putreg(0x0F, VIC_VECTPRIORITY0_OFFSET + (reg << 2));
}
/* currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL;
/* Enable global ARM interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
irqrestore(SVC_MODE | PSR_F_BIT);
#endif
}
void up_attach_vector(int irq, int vector, vic_vector_t handler)
{
/* Verify that the IRQ number and vector number are within range */
if (irq < NR_IRQS && vector < 32 && handler)
{
int offset = vector << 2;
/* Disable all interrupts */
irqstate_t flags = irqsave();
/* Save the vector address */
vic_putreg((uint32_t)handler, VIC_VECTADDR0_OFFSET + offset);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(irq, PRIORITY_HIGHEST);
#endif
/* Enable the vectored interrupt */
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
irqrestore(flags);
}
}
int up_timerisr(int irq, uint32_t * regs)
#endif
{
static uint32_t tick;
/* Process timer interrupt */
sched_process_timer();
/* Clear the MR0 match interrupt */
tmr_putreg8(TMR_IR_MR0I, TMR_IR_OFFSET);
/* Reset the VIC as well */
#ifdef CONFIG_VECTORED_INTERRUPTS
/* write any value to VICAddress to acknowledge the interrupt */
vic_putreg(0, VIC_ADDRESS_OFFSET);
#endif
if (tick++ > 100)
{
tick = 0;
up_statledoff();
}
else
up_statledon();
return 0;
}
int up_prioritize_irq(int irq, int priority)
{
/* The default priority on reset is 16 */
if (irq < NR_IRQS && priority > 0 && priority < 16)
{
int offset = irq << 2;
vic_putreg(priority, VIC_VECTPRIORITY0_OFFSET + offset);
return OK;
}
return -EINVAL;
}
void up_detach_vector(int vector)
{
/* Verify that the vector number is within range */
if (vector < 32)
{
/* Disable the vectored interrupt */
int offset = vector << 2;
vic_putreg(0, (VIC_VECTADDR0_OFFSET + offset));
}
}
void up_detach_vector(int vector)
{
/* Verify that the vector number is within range */
if (vector < 16)
{
/* Disable the vectored interrupt */
int offset = vector << 2;
vic_putreg(0, LPC214X_VIC_VECTCNTL0_OFFSET + offset);
}
}
void up_maskack_irq(int irq)
{
uint32_t reg32;
if ((unsigned)irq < NR_IRQS)
{
/* Mask the IRQ by clearing the associated bit in Software Priority Mask
* register
*/
reg32 = vic_getreg(VIC_PRIORITY_MASK_OFFSET);
reg32 &= ~(1 << irq);
vic_putreg(reg32, VIC_PRIORITY_MASK_OFFSET);
}
/* Clear interrupt */
vic_putreg((1 << irq), VIC_SOFTINTCLEAR_OFFSET);
#ifdef CONFIG_VECTORED_INTERRUPTS
vic_putreg(0, VIC_ADDRESS_OFFSET); /* dummy write to clear VICADDRESS */
#endif
}
void up_disable_irq(int irq)
{
/* Verify that the IRQ number is within range */
if (irq < NR_IRQS)
{
/* Disable the irq by setting the corresponding bit in the VIC Interrupt
* Enable Clear register.
*/
vic_putreg((1 << irq), VIC_INTENCLEAR_OFFSET);
}
}
void up_irqinitialize(void)
{
int reg;
/* Disable all interrupts. We do this by writing zero to the IntEnable
* register. This is equivalent to writing all ones to the IntClearEnable
* register.
*/
vic_putreg(0, LPC214X_VIC_INTENABLE_OFFSET);
/* Select all IRQs, no FIQs */
vic_putreg(0, LPC214X_VIC_INTSELECT_OFFSET);
/* Set the default vector */
vic_putreg((uint32_t)up_decodeirq, LPC214X_VIC_DEFVECTADDR_OFFSET);
/* Disable all vectored interrupts */
for (reg = LPC214X_VIC_VECTCNTL0_OFFSET;
reg <= LPC214X_VIC_VECTCNTL15_OFFSET;
reg += 4)
{
vic_putreg(0, reg);
}
/* currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL;
/* And finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_INTERRUPTS
irqrestore(SVC_MODE | PSR_F_BIT);
#endif
}
void up_attach_vector(int irq, int vector, vic_vector_t handler)
{
/* Verify that the IRQ number and vector number are within range */
if (irq < NR_IRQS && vector < 16 && handler)
{
int offset = vector << 2;
/* Disable all interrupts */
irqstate_t flags = irqsave();
/* Save the vector address */
vic_putreg((uint32_t)handler, LPC214X_VIC_VECTADDR0_OFFSET + offset);
/* Enable the vectored interrupt */
vic_putreg(((irq << LPC214X_VECTCNTL_IRQSHIFT) | LPC214X_VECTCNTL_ENABLE),
LPC214X_VIC_VECTCNTL0_OFFSET + offset);
irqrestore(flags);
}
}
int up_timerisr(int irq, uint32_t *regs)
#endif
{
/* Process timer interrupt */
sched_process_timer();
/* Clear the MR0 match interrupt */
tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET);
/* Reset the VIC as well */
#ifdef CONFIG_VECTORED_INTERRUPTS
vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET);
#endif
return 0;
}
void up_enable_irq(int irq)
{
/* Verify that the IRQ number is within range */
if (irq < NR_IRQS)
{
/* Disable all interrupts */
irqstate_t flags = irqsave();
/* Enable the irq by setting the corresponding bit in the VIC Interrupt
* Enable register.
*/
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);
vic_putreg(val | (1 << irq), VIC_INTENABLE_OFFSET);
irqrestore(flags);
}
}
/***********************************************************************
* Name: up_disable_irq_protect
* VIC registers can only be accessed in privileged mode
***********************************************************************/
#if 0 /* Not used */
static void up_disable_irq_protect(void)
{
vic_putreg(0, VIC_PROTECTION_OFFSET);
}
static void up_enable_irq_protect(void)
{
// ~ uint32_t reg32 = vic_getreg(VIC_PROTECTION_OFFSET);
// ~ reg32 &= ~(0xFFFFFFFF);
vic_putreg(0x01, VIC_PROTECTION_OFFSET);
}
