static void band_gap_reset(struct drm_i915_private *dev_priv) { mutex_lock(&dev_priv->dpio_lock); vlv_flisdsi_write(dev_priv, 0x08, 0x0001); vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); udelay(150); vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); vlv_flisdsi_write(dev_priv, 0x08, 0x0000); mutex_unlock(&dev_priv->dpio_lock); }
static void intel_dsi_device_ready(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); int pipe = intel_crtc->pipe; u32 val; DRM_DEBUG_KMS("\n"); mutex_lock(&dev_priv->dpio_lock); /* program rcomp for compliance, reduce from 50 ohms to 45 ohms * needed everytime after power gate */ vlv_flisdsi_write(dev_priv, 0x04, 0x0004); mutex_unlock(&dev_priv->dpio_lock); /* bandgap reset is needed after everytime we do power gate */ band_gap_reset(dev_priv); I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); usleep_range(2500, 3000); val = I915_READ(MIPI_PORT_CTRL(pipe)); I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); usleep_range(1000, 1500); I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); usleep_range(2500, 3000); I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); usleep_range(2500, 3000); }