void *
AcpiOsMapMemory (
ACPI_PHYSICAL_ADDRESS where, /* not page aligned */
ACPI_SIZE length) /* in bytes, not page-aligned */
{
return vm_map_phys(SELF, (void *) where, length);
}
struct uio_mem *
uio_map_iomem(struct uio_handle *handle, const char *name,
paddr_t phys, size_t size)
{
struct uio_mem *mem;
int ret;
mem = malloc(sizeof(struct uio_mem));
if (!mem)
return NULL;
mem->phys_addr = phys;
mem->size = size;
strncpy(mem->name, name, sizeof(name));
ret = vm_map_phys(phys, size, &mem->addr);
if (ret < 0)
goto out_free_mem;
ret = vm_attribute(task_self(), mem->addr, PROT_IO);
if (ret < 0)
goto out_free_mem;
list_init(&mem->link);
list_insert(&handle->mem, &mem->link);
return mem;
out_free_mem:
free(mem);
return NULL;
}
char *vt_init(vt_info_t *vi_p) {
int r;
struct mem_range mr;
/* Allow memory mapping */
mr.mr_base = (phys_bytes)(vi_p->vram_base);
mr.mr_limit = mr.mr_base + vi_p->vram_size;
if( OK != (r = sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr)))
panic("video_txt: sys_privctl (ADD_MEM) failed: %d\n", r);
/* Map memory */
video_mem = vm_map_phys(SELF, (void *)mr.mr_base, vi_p->vram_size);
if(video_mem == MAP_FAILED)
panic("video_txt couldn't map video memory");
/* Save text mode resolution */
scr_lines = vi_p->scr_lines;
scr_width = vi_p->scr_width;
return video_mem;
}
void *vg_init(unsigned short mode)
{
struct reg86u reg86;
reg86.u.b.intno = VBE_INTERRUPT_VECTOR; /* BIOS video services */
reg86.u.b.ah = VBE_FUNCTION;
reg86.u.b.al = VBE_SET_VBE_MODE;
reg86.u.w.bx = mode | BIT(VBE_MODE_NUMBER_LINEAR_FLAT_FRAME_BUFFER_BIT);
vbe_mode_info_t vbe_mode_info;
if (sys_int86(®86) == OK)
{
if (reg86.u.w.ax == VBE_FUNCTION_SUPPORTED | VBE_FUNCTION_CALL_SUCCESSFUL)
{
if(vbe_get_mode_info(mode, &vbe_mode_info))
{
return NULL;
}
else
{
int r;
struct mem_range mr;
unsigned mr_size;
h_res = vbe_mode_info.XResolution;
v_res = vbe_mode_info.YResolution;
bits_per_pixel = vbe_mode_info.BitsPerPixel;
/* Allow memory mapping */
mr.mr_base = vbe_mode_info.PhysBasePtr;
mr_size = h_res * v_res * bits_per_pixel;
mr.mr_limit = mr.mr_base + mr_size;
if(sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr))
{
return NULL;
}
/* Map memory */
video_mem = vm_map_phys(SELF, (void *)mr.mr_base, mr_size);
if(video_mem != MAP_FAILED)
{
if ((double_buffer = malloc(h_res * v_res * bits_per_pixel / 8)) != NULL)
{
if ((mouse_buffer = malloc(h_res * v_res * bits_per_pixel / 8)) != NULL)
{
return video_mem;
}
}
}
}
}
}
return NULL;
}
void* vg_init(unsigned short mode) {
struct mem_range mr;
vbe_mode_info_t vmi_p;
struct reg86u reg86;
reg86.u.b.intno = BIOS_VIDEO;
reg86.u.b.ah = VBE;
reg86.u.b.al = SET_VBE;
reg86.u.w.bx = BIT(LINEAR_BIT) | mode;
if (sys_int86(®86)) {
printf("vg_init()::bios call didn't return 0\n");
return NULL;
}
if (vbe_get_mode_info(mode, &vmi_p) == -1) {
printf("vg_init()::failed in vbe_get_mode_info");
return NULL;
}
h_res = vmi_p.XResolution;
v_res = vmi_p.YResolution;
bits_per_pixel = vmi_p.BitsPerPixel;
if (bits_per_pixel / 8 > 0)
bytes_per_pixel = bits_per_pixel / 8;
else
bytes_per_pixel = 1;
vram_size = h_res * v_res * bytes_per_pixel;
int r;
/* Allow memory mapping */
mr.mr_base = vmi_p.PhysBasePtr;
mr.mr_limit = mr.mr_base + vram_size;
if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) {
panic("video_txt: sys_privctl (ADD_MEM) failed: %d\n", r);
return NULL;
}
/* Map memory */
video_mem = vm_map_phys(SELF, (void *) mr.mr_base, vram_size);
buffer = malloc(vram_size);
if (video_mem == MAP_FAILED) {
panic("video_txt couldn't map video memory");
return NULL;
}
return video_mem;
}
//maps buffer at base base, size size to proccess's virtual memory,
void* map_virtual_memory(unsigned long base, unsigned long size, void** ptr)
{
int r;
struct mem_range mr;
mr.mr_base = (phys_bytes)(base);
mr.mr_limit = mr.mr_base + size;
if( OK != (r = sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr)))
panic("video_txt: sys_privctl (ADD_MEM) failed: %d\n", r);
*ptr = vm_map_phys(SELF, (void *)mr.mr_base, size);
if(*ptr == MAP_FAILED)
panic("video_gr couldn't map video memory");
return *ptr;
}
void *__mem_alloc_pages(void *base, int nr, int size,
struct bitmask *mask, int numa_policy)
{
void *vaddr;
int flags = MAP_PRIVATE | MAP_ANONYMOUS;
size_t len = nr * size;
switch (size) {
case PGSIZE_4KB:
break;
case PGSIZE_2MB:
flags |= MAP_HUGETLB | MAP_FIXED;
#ifdef MAP_HUGE_2MB
flags |= MAP_HUGE_2MB;
#endif
break;
case PGSIZE_1GB:
#ifdef MAP_HUGE_1GB
flags |= MAP_HUGETLB | MAP_HUGE_1GB | MAP_FIXED;
#else
return MAP_FAILED;
#endif
break;
default: /* fail on other sizes */
return MAP_FAILED;
}
vaddr = mmap(base, len, PROT_READ | PROT_WRITE, flags, -1, 0);
if (vaddr == MAP_FAILED)
return MAP_FAILED;
if (mbind(vaddr, len, numa_policy, mask ? mask->maskp : NULL,
mask ? mask->size : 0, MPOL_MF_STRICT))
goto fail;
if (vm_map_phys((physaddr_t) vaddr, (virtaddr_t) vaddr, nr, size,
VM_PERM_R | VM_PERM_W))
goto fail;
sighandler_t s = signal(SIGBUS, sigbus_error);
*(uint64_t *)vaddr = 0;
signal(SIGBUS, s);
return vaddr;
fail:
munmap(vaddr, len);
return MAP_FAILED;
}
void *
AcpiOsMapMemory (
ACPI_PHYSICAL_ADDRESS where, /* not page aligned */
ACPI_SIZE length) /* in bytes, not page-aligned */
{
ACPI_PHYSICAL_ADDRESS addr;
void * vir;
unsigned sdiff;
addr = where & ~0xfff; /* align to 4k */
sdiff = where - addr;
vir = vm_map_phys(SELF, (void *) addr, length + sdiff);
return (void *) ((char *)vir + sdiff);
}
void *vg_init(unsigned short mode) {
vbe_mode_info_t config;
if ( vbe_set_mode(VBE_MODE, mode) == 1) //set graphic mode
return NULL;
if (vbe_get_mode_info(mode, &config) != 0) //get vbe info
{
return NULL;
}
h_res = config.XResolution; //store X Resolution
v_res = config.YResolution; //store Y Resolution
bits_per_pixel = config.BitsPerPixel; //store Bits Per Pixel
vram_size = (config.XResolution * config.YResolution * config.BitsPerPixel) / 8; //store the size of the vram
int r;
struct mem_range mr;
/* Allow memory mapping */
mr.mr_base = (config.PhysBasePtr);
mr.mr_limit = mr.mr_base + (config.XResolution * config.YResolution * config.BitsPerPixel) / 8;
if( OK != (r = sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr)))
panic("video_txt: sys_privctl (ADD_MEM) failed: %d\n", r);
/* Map memory */
video_mem = vm_map_phys(SELF, (void *)mr.mr_base, (config.XResolution * config.YResolution * config.BitsPerPixel) / 8);
if(video_mem == MAP_FAILED)
panic("video_txt couldn't map video memory");
if (video_mem == NULL)
{
printf("vg_init: Error!\n");
vg_exit();
return NULL;
}
return config.PhysBasePtr;
}
void * vg_init(unsigned long mode) {
struct reg86u r;
r.u.w.ax = 0x4F02; // VBE call, function 02 -- set VBE mode -- ah:0x4F invoking VBE function, al:0x02 function being called:set VBE mode
r.u.w.bx = 1<<14|mode; // set bit 14: linear framebuffer
r.u.b.intno = 0x10;
if( sys_int86(&r) != OK ) {
printf("set_vbe_mode: sys_int86() failed \n");
}
/*
vbe_mode_info_t info;
if(vbe_get_mode_info(mode,&info)==1)
printf("error in vbe_get_mode \n");
h_res=info.XResolution;
v_res=info.YResolution;
bits_per_pixel=info.BitsPerPixel;
*video_mem=info.PhysBasePtr;*/
h_res=H_RES;
v_res=V_RES;
bits_per_pixel=BITS_PER_PIXEL;
bytes_per_pixel=bits_per_pixel/8;
int y;
struct mem_range mr;
/* Allow memory mapping */
mr.mr_base = VRAM_PHYS_ADDR;
mr.mr_limit = mr.mr_base + h_res*v_res;
if( OK != (y = sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr)))
panic("video_txt: sys_privctl (ADD_MEM) failed: %d\n", y);
/* Map memory */
video_mem = vm_map_phys(SELF, (void *)mr.mr_base, h_res*v_res);
if(video_mem == MAP_FAILED) panic("video_txt couldn't map video memory");
return NULL;
}
/*===========================================================================*
* atl2_init *
*===========================================================================*/
static void atl2_init(int devind)
{
/* Initialize the device.
*/
u32_t bar;
int r, flag;
/* Initialize global state. */
state.devind = devind;
state.mode = DL_NOMODE;
state.flags = 0;
state.recv_count = 0;
memset(&state.stat, 0, sizeof(state.stat));
if ((r = pci_get_bar(devind, PCI_BAR, &bar, &state.size, &flag)) != OK)
panic("unable to retrieve bar: %d", r);
if (state.size < ATL2_MIN_MMAP_SIZE || flag)
panic("invalid register bar");
state.base = vm_map_phys(SELF, (void *) bar, state.size);
if (state.base == MAP_FAILED)
panic("unable to map in registers");
if ((r = atl2_alloc_dma()) != OK)
panic("unable to allocate DMA buffers: %d", r);
state.irq = pci_attr_r8(devind, PCI_ILR);
if ((r = sys_irqsetpolicy(state.irq, 0, &state.hook_id)) != OK)
panic("unable to register IRQ: %d", r);
if (!atl2_reset())
panic("unable to reset hardware");
if ((r = sys_irqenable(&state.hook_id)) != OK)
panic("unable to enable IRQ: %d", r);
atl2_get_hwaddr();
atl2_setup();
}
/*===========================================================================*
* sef_cb_init_fresh *
*===========================================================================*/
static int sef_cb_init_fresh(int UNUSED(type), sef_init_info_t *UNUSED(info))
{
/* Initialize the memory driver. */
int i;
#if 0
struct kinfo kinfo; /* kernel information */
int s;
if (OK != (s=sys_getkinfo(&kinfo))) {
panic("Couldn't get kernel information: %d", s);
}
/* Map in kernel memory for /dev/kmem. */
m_geom[KMEM_DEV].dv_base = cvul64(kinfo.kmem_base);
m_geom[KMEM_DEV].dv_size = cvul64(kinfo.kmem_size);
if((m_vaddrs[KMEM_DEV] = vm_map_phys(SELF, (void *) kinfo.kmem_base,
kinfo.kmem_size)) == MAP_FAILED) {
printf("MEM: Couldn't map in /dev/kmem.");
}
#endif
/* Ramdisk image built into the memory driver */
m_geom[IMGRD_DEV].dv_base= cvul64(0);
m_geom[IMGRD_DEV].dv_size= cvul64(imgrd_size);
m_vaddrs[IMGRD_DEV] = (vir_bytes) imgrd;
/* Initialize /dev/zero. Simply write zeros into the buffer. */
for (i=0; i<ZERO_BUF_SIZE; i++) {
dev_zero[i] = '\0';
}
for(i = 0; i < NR_DEVS; i++)
openct[i] = 0;
/* Set up memory range for /dev/mem. */
m_geom[MEM_DEV].dv_base = cvul64(0);
m_geom[MEM_DEV].dv_size = cvul64(0xffffffff);
m_vaddrs[MEM_DEV] = (vir_bytes) MAP_FAILED; /* we are not mapping this in. */
return(OK);
}
/*
* Map flash memory. This step is optional.
*/
static void
e1000_map_flash(e1000_t * e, int devind, int did)
{
u32_t flash_addr, gfpreg, sector_base_addr;
size_t flash_size;
/* The flash memory is pointed to by BAR2. It may not be present. */
if ((flash_addr = pci_attr_r32(devind, PCI_BAR_2)) == 0)
return;
/* The default flash size. */
flash_size = 0x10000;
switch (did) {
case E1000_DEV_ID_82540EM:
case E1000_DEV_ID_82545EM:
case E1000_DEV_ID_82540EP:
case E1000_DEV_ID_82540EP_LP:
return; /* don't even try */
/* 82566/82567/82562V series support mapping 4kB of flash memory. */
case E1000_DEV_ID_ICH10_D_BM_LM:
case E1000_DEV_ID_ICH10_R_BM_LF:
flash_size = 0x1000;
break;
}
e->flash = vm_map_phys(SELF, (void *)flash_addr, flash_size);
if (e->flash == MAP_FAILED)
panic("e1000: couldn't map in flash");
/* sector_base_addr is a "sector"-aligned address (4096 bytes). */
gfpreg = E1000_READ_FLASH_REG(e, ICH_FLASH_GFPREG);
sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
/* flash_base_addr is byte-aligned. */
e->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
}
/*===========================================================================*
* m_transfer *
*===========================================================================*/
static int m_transfer(
endpoint_t endpt, /* endpoint of grant owner */
int opcode, /* DEV_GATHER_S or DEV_SCATTER_S */
u64_t pos64, /* offset on device to read or write */
iovec_t *iov, /* pointer to read or write request vector */
unsigned int nr_req, /* length of request vector */
endpoint_t UNUSED(user_endpt),/* endpoint of user process */
unsigned int UNUSED(flags)
)
{
/* Read or write one the driver's character devices. */
unsigned count, left, chunk;
vir_bytes vir_offset = 0;
struct device *dv;
unsigned long dv_size;
int s, r;
off_t position;
cp_grant_id_t grant;
vir_bytes dev_vaddr;
/* ZERO_DEV and NULL_DEV are infinite in size. */
if (m_device != ZERO_DEV && m_device != NULL_DEV && ex64hi(pos64) != 0)
return OK; /* Beyond EOF */
position= cv64ul(pos64);
/* Get minor device number and check for /dev/null. */
dv = &m_geom[m_device];
dv_size = cv64ul(dv->dv_size);
dev_vaddr = m_vaddrs[m_device];
while (nr_req > 0) {
/* How much to transfer and where to / from. */
count = iov->iov_size;
grant = (cp_grant_id_t) iov->iov_addr;
switch (m_device) {
/* No copying; ignore request. */
case NULL_DEV:
if (opcode == DEV_GATHER_S) return(OK); /* always at EOF */
break;
/* Virtual copying. For kernel memory. */
default:
case KMEM_DEV:
if(!dev_vaddr || dev_vaddr == (vir_bytes) MAP_FAILED) {
printf("MEM: dev %d not initialized\n", m_device);
return EIO;
}
if (position >= dv_size) return(OK); /* check for EOF */
if (position + count > dv_size) count = dv_size - position;
if (opcode == DEV_GATHER_S) { /* copy actual data */
r=sys_safecopyto(endpt, grant, vir_offset,
dev_vaddr + position, count);
} else {
r=sys_safecopyfrom(endpt, grant, vir_offset,
dev_vaddr + position, count);
}
if(r != OK) {
panic("I/O copy failed: %d", r);
}
break;
/* Physical copying. Only used to access entire memory.
* Transfer one 'page window' at a time.
*/
case MEM_DEV:
{
u32_t pagestart, page_off;
static u32_t pagestart_mapped;
static int any_mapped = 0;
static char *vaddr;
int r;
u32_t subcount;
phys_bytes mem_phys;
if (position >= dv_size)
return(OK); /* check for EOF */
if (position + count > dv_size)
count = dv_size - position;
mem_phys = position;
page_off = mem_phys % PAGE_SIZE;
pagestart = mem_phys - page_off;
/* All memory to the map call has to be page-aligned.
* Don't have to map same page over and over.
*/
if(!any_mapped || pagestart_mapped != pagestart) {
if(any_mapped) {
if(vm_unmap_phys(SELF, vaddr, PAGE_SIZE) != OK)
panic("vm_unmap_phys failed");
any_mapped = 0;
}
vaddr = vm_map_phys(SELF, (void *) pagestart, PAGE_SIZE);
if(vaddr == MAP_FAILED)
r = ENOMEM;
else
r = OK;
if(r != OK) {
printf("memory: vm_map_phys failed\n");
return r;
}
any_mapped = 1;
pagestart_mapped = pagestart;
}
/* how much to be done within this page. */
subcount = PAGE_SIZE-page_off;
if(subcount > count)
subcount = count;
if (opcode == DEV_GATHER_S) { /* copy data */
s=sys_safecopyto(endpt, grant,
vir_offset, (vir_bytes) vaddr+page_off, subcount);
} else {
s=sys_safecopyfrom(endpt, grant,
vir_offset, (vir_bytes) vaddr+page_off, subcount);
}
if(s != OK)
return s;
count = subcount;
break;
}
/* Null byte stream generator. */
case ZERO_DEV:
if (opcode == DEV_GATHER_S) {
size_t suboffset = 0;
left = count;
while (left > 0) {
chunk = (left > ZERO_BUF_SIZE) ? ZERO_BUF_SIZE : left;
s=sys_safecopyto(endpt, grant,
vir_offset+suboffset, (vir_bytes) dev_zero, chunk);
if(s != OK)
return s;
left -= chunk;
suboffset += chunk;
}
}
break;
}
/* Book the number of bytes transferred. */
position += count;
vir_offset += count;
if ((iov->iov_size -= count) == 0) { iov++; nr_req--; vir_offset = 0; }
}
return(OK);
}
void * vg_init(unsigned long mode) {
// -----------------------
// -Non-Hardcoded Version-
// -----------------------
struct reg86u reg86;
vbe_mode_info_t vmi;
int r;
struct mem_range mr;
reg86.u.w.ax = 0x4F02;
reg86.u.w.bx = 1<<14|mode;
reg86.u.b.intno = 0x10;
if(sys_int86(®86) != OK) {
printf("set_vbe_mode: sys_int86() failed\n");
return NULL;
}
else {
vbe_get_mode_info(mode, &vmi);
h_res = vmi.XResolution;
v_res = vmi.YResolution;
bits_per_pixel = vmi.BitsPerPixel;
mr.mr_base = vmi.PhysBasePtr;
mr.mr_limit = mr.mr_base + (h_res * v_res * (bits_per_pixel / 8));
if((r = sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr)) != OK) {
panic("vg_init: sys_privctl (ADD_MEM) failed: %d\n", r);
return NULL;
}
else {
video_mem = vm_map_phys(SELF, (void *)mr.mr_base, (h_res * v_res * (bits_per_pixel / 8)));
if(video_mem == MAP_FAILED){
panic("vg_init: Couldn't map video memory!\n");
return NULL;
} else
return video_mem;
}
}
// -------------------
// -Hardcoded Version-
// -------------------
/*
struct reg86u reg86;
vbe_mode_info_t vmi;
int r;
struct mem_range mr;
reg86.u.w.ax = 0x4F02;
reg86.u.w.bx = 1<<14|mode;
reg86.u.b.intno = 0x10;
if(sys_int86(®86) != OK) {
printf("set_vbe_mode: sys_int86() failed\n");
return NULL;
}
else {
h_res = H_RES;
v_res = V_RES;
bits_per_pixel = BITS_PER_PIXEL;
mr.mr_base = VRAM_PHYS_ADDR;
mr.mr_limit = mr.mr_base + (h_res * v_res * (bits_per_pixel / 8));
if((r = sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr)) != OK) {
panic("vg_init: sys_privctl (ADD_MEM) failed: %d\n", r);
return NULL;
}
else {
video_mem = vm_map_phys(SELF, (void *)mr.mr_base, (h_res * v_res * (bits_per_pixel / 8)));
if(video_mem == MAP_FAILED){
panic("vg_init: Couldn't map video memory!\n");
return NULL;
} else
return video_mem;
}
}*/
}
/*============================================================================*
* lan8710a_map_regs *
*============================================================================*/
static void
lan8710a_map_regs(void)
{
struct minix_mem_range mr;
mr.mr_base = CM_PER_BASE_ADR;
mr.mr_limit = CM_PER_BASE_ADR + MEMORY_LIMIT;
if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) {
panic("Unable to request permission to map memory");
}
lan8710a_state.regs_cp_per =
(vir_bytes)vm_map_phys(SELF, (void *)CM_PER_BASE_ADR, 512);
if ((void *)lan8710a_state.regs_cp_per == MAP_FAILED) {
panic("lan8710a_state.regs_cp_per: vm_map_phys failed");
}
lan8710a_state.regs_cpdma_stram =
(vir_bytes)vm_map_phys(SELF, (void *)CPDMA_STRAM_BASE_ADR, 512);
if ((void *)lan8710a_state.regs_cpdma_stram == MAP_FAILED) {
panic("lan8710a_state.regs_cpdma_stram: vm_map_phys failed");
}
lan8710a_state.regs_cpsw_cpdma =
(vir_bytes)vm_map_phys(SELF, (void *)CPSW_CPDMA_BASE_ADR, 512);
if ((void *)lan8710a_state.regs_cpsw_cpdma == MAP_FAILED) {
panic("lan8710a_state.regs_cpsw_cpdma: vm_map_phys failed");
}
lan8710a_state.regs_cpsw_ale =
(vir_bytes)vm_map_phys(SELF, (void *)CPSW_ALE_BASE_ADR, 256);
if ((void *)lan8710a_state.regs_cpsw_ale == MAP_FAILED) {
panic("lan8710a_state.regs_cpsw_ale: vm_map_phys failed");
}
lan8710a_state.regs_cpsw_sl =
(vir_bytes)vm_map_phys(SELF, (void *)CPSW_SL_BASE_ADR, 512);
if ((void *)lan8710a_state.regs_cpsw_sl == MAP_FAILED) {
panic("lan8710a_state.regs_cpsw_sl: vm_map_phys failed");
}
lan8710a_state.regs_cpsw_ss =
(vir_bytes)vm_map_phys(SELF, (void *)CPSW_SS_BASE_ADR, 512);
if ((void *)lan8710a_state.regs_cpsw_ss == MAP_FAILED) {
panic("lan8710a_state.regs_cpsw_ss: vm_map_phys failed");
}
lan8710a_state.regs_cpsw_wr =
(vir_bytes)vm_map_phys(SELF, (void *)CPSW_WR_BASE_ADR, 512);
if ((void *)lan8710a_state.regs_cpsw_wr == MAP_FAILED) {
panic("lan8710a_state.regs_cpsw_wr: vm_map_phys failed");
}
lan8710a_state.regs_ctrl_mod =
(vir_bytes)vm_map_phys(SELF, (void *)CTRL_MOD_BASE_ADR, 2560);
if ((void *)lan8710a_state.regs_ctrl_mod == MAP_FAILED) {
panic("lan8710a_state.regs_ctrl_mod: vm_map_phys failed");
}
lan8710a_state.regs_intc =
(vir_bytes)vm_map_phys(SELF, (void *)INTC_BASE_ADR, 512);
if ((void *)lan8710a_state.regs_intc == MAP_FAILED) {
panic("lan8710a_state.regs_intc: vm_map_phys failed");
}
lan8710a_state.regs_mdio =
(vir_bytes)vm_map_phys(SELF, (void *)MDIO_BASE_ADDR, 512);
if ((void *)lan8710a_state.regs_mdio == MAP_FAILED) {
panic("lan8710a_state.regs_mdio: vm_map_phys failed");
}
mr.mr_base = BEGINNING_DESC_MEM;
mr.mr_limit = BEGINNING_DESC_MEM + DESC_MEMORY_LIMIT;
if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) {
panic("Unable to request permission to map memory");
}
lan8710a_state.rx_desc_phy = BEGINNING_RX_DESC_MEM;
lan8710a_state.tx_desc_phy = BEGINNING_TX_DESC_MEM;
lan8710a_state.rx_desc = (lan8710a_desc_t *)vm_map_phys(SELF,
(void *)lan8710a_state.rx_desc_phy, 1024);
if ((void *)lan8710a_state.rx_desc == MAP_FAILED) {
panic("lan8710a_state.rx_desc: vm_map_phys failed");
}
lan8710a_state.tx_desc = (lan8710a_desc_t *)vm_map_phys(SELF,
(void *)lan8710a_state.tx_desc_phy, 1024);
if ((void *)lan8710a_state.tx_desc == MAP_FAILED) {
panic("lan8710a_state.tx_desc: vm_map_phys failed");
}
mr.mr_base = CPSW_STATS_BASE_ADR;
mr.mr_limit = CPSW_STATS_BASE_ADR + CPSW_STATS_MEM_LIMIT;
if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) {
panic("Unable to request permission to map memory");
}
lan8710a_state.regs_cpsw_stats =
(vir_bytes)vm_map_phys(SELF, (void *)CPSW_STATS_BASE_ADR, 256);
if ((void *)lan8710a_state.regs_cpsw_stats == MAP_FAILED) {
panic("lan8710a_state.regs_cpsw_stats: vm_map_phys failed");
}
}
void *vg_init(unsigned short mode) {
vbe_mode_info_t info;
struct reg86u reg86;
int r;
struct mem_range mr;
reg86.u.b.intno = BIOS_VIDEO_INT; /* BIOS video services */
reg86.u.w.ax = SET_VBE_MODE; /* Set Video Mode function */
reg86.u.w.bx = SET_LINEAR_MODE | mode; /* Mode */
if (sys_int86(®86) != OK) { // Sets video mode
printf("\tvg_init(): sys_int86() failed \n");
return NULL;
}
switch (reg86.u.w.ax) {
case VBE_FUNC_CALL_FAILED:
printf("\tvg_init(): sys_int86() function call failed.\n");
return NULL;
break;
case VBE_FUNC_NOT_SUPPORTED:
printf("\tvg_init(): sys_int86() function not supported.\n");
return NULL;
break;
case VBE_FUNC_INVALID_CUR_MODE:
printf(
"\tvg_init(): sys_int86() function invalid in current video mode.\n");
return NULL;
break;
}
if (lm_init() == NULL) {
printf("\tvg_init(): lm_init() failed \n");
return NULL;
}
if (vbe_get_mode_info(mode, &info) != OK) { // Gets info
printf("\tvg_init(): vbe_get_mode_info() failed \n");
return NULL;
}
h_res = info.XResolution;
v_res = info.YResolution; //Sets global variables
bits_per_pixel = info.BitsPerPixel;
//Allow memory mapping
mr.mr_base = (phys_bytes)(info.PhysBasePtr);
mr.mr_limit = mr.mr_base
+ info.XResolution * info.YResolution * info.BitsPerPixel / 8;
if (OK != (r = sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr)))
panic("video_txt: sys_privctl (ADD_MEM) failed: %d\n", r);
// Map memory
video_mem = vm_map_phys(SELF, (void *) mr.mr_base,
info.XResolution * info.YResolution * info.BitsPerPixel / 8);
double_buffer = malloc(h_res * v_res * sizeof(char));
/*if(video_mem == MAP_FAILED)
panic("video_txt couldn't map video memory");*/
return video_mem;
}
/*===========================================================================*
* e1000_probe *
*===========================================================================*/
PRIVATE int e1000_probe(e1000_t *e, int skip)
{
int i, r, devind;
u16_t vid, did;
u32_t status[2];
u32_t gfpreg, sector_base_addr;
char *dname;
E1000_DEBUG(3, ("%s: probe()\n", e->name));
/*
* Attempt to iterate the PCI bus. Start at the beginning.
*/
if ((r = pci_first_dev(&devind, &vid, &did)) == 0)
{
return FALSE;
}
/* Loop devices on the PCI bus. */
for(;;)
{
for (i = 0; pcitab_e1000[i] != 0; i++)
{
if (vid != 0x8086)
continue;
if (did != pcitab_e1000[i])
continue;
else
break;
}
if (pcitab_e1000[i] != 0)
{
if (!skip)
break;
skip--;
}
if (!(r = pci_next_dev(&devind, &vid, &did)))
{
return FALSE;
}
}
/*
* Successfully detected an Intel Pro/1000 on the PCI bus.
*/
e->status |= E1000_DETECTED;
e->eeprom_read = eeprom_eerd;
/*
* Set card specific properties.
*/
switch (did)
{
case E1000_DEV_ID_ICH10_R_BM_LF:
e->eeprom_read = eeprom_ich;
break;
case E1000_DEV_ID_82574L:
case E1000_DEV_ID_82541GI_LF:
e->eeprom_done_bit = (1 << 1);
e->eeprom_addr_off = 2;
break;
default:
e->eeprom_done_bit = (1 << 4);
e->eeprom_addr_off = 8;
break;
}
/* Inform the user about the new card. */
if (!(dname = pci_dev_name(vid, did)))
{
dname = "Intel Pro/1000 Gigabit Ethernet Card";
}
E1000_DEBUG(1, ("%s: %s (%04x/%04x/%02x) at %s\n",
e->name, dname, vid, did, e->revision,
pci_slot_name(devind)));
/* Reserve PCI resources found. */
if ((r = pci_reserve_ok(devind)) != OK)
{
panic("failed to reserve PCI device: %d", r);
}
/* Read PCI configuration. */
e->irq = pci_attr_r8(devind, PCI_ILR);
e->regs = vm_map_phys(SELF, (void *) pci_attr_r32(devind, PCI_BAR),
0x20000);
/* Verify mapped registers. */
if (e->regs == (u8_t *) -1) {
panic("failed to map hardware registers from PCI");
}
/* Optionally map flash memory. */
if (did != E1000_DEV_ID_82540EM &&
did != E1000_DEV_ID_82540EP &&
pci_attr_r32(devind, PCI_BAR_2))
{
if((e->flash = vm_map_phys(SELF,
(void *) pci_attr_r32(devind, PCI_BAR_2), 0x10000)) == MAP_FAILED) {
if((e->flash = vm_map_phys(SELF,
(void *) pci_attr_r32(devind, PCI_BAR_2), 0x1000))
== MAP_FAILED) {
panic("e1000: couldn't map in flash.");
}
}
gfpreg = E1000_READ_FLASH_REG(e, ICH_FLASH_GFPREG);
/*
* sector_base_addr is a "sector"-aligned address (4096 bytes)
*/
sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
/* flash_base_addr is byte-aligned */
e->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
}
/*
* Output debug information.
*/
status[0] = e1000_reg_read(e, E1000_REG_STATUS);
E1000_DEBUG(3, ("%s: MEM at %p, IRQ %d\n",
e->name, e->regs, e->irq));
E1000_DEBUG(3, ("%s: link %s, %s duplex\n",
e->name, status[0] & 3 ? "up" : "down",
status[0] & 1 ? "full" : "half"));
return TRUE;
}
void *vg_init(unsigned short mode)
{
struct reg86u r;
vbe_mode_info_t *info = malloc(sizeof(vbe_mode_info_t));
if (vbe_get_mode_info(mode, info) != 0)
{
return NULL;
}
h_res=info->XResolution;
v_res=info->YResolution;
bits_per_pixel=info->BitsPerPixel;
printf("%d\n", h_res);
int erro;
struct mem_range mr;
/* Allow memory mapping */
unsigned int vram_size = h_res * v_res * (bits_per_pixel/8);
mr.mr_base = (phys_bytes)(info->PhysBasePtr);
mr.mr_limit = mr.mr_base + vram_size;
if( OK != (erro = sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr)))
panic("video_gr: sys_privctl (ADD_MEM) failed: %d\n", erro);
/* Map memory */
video_mem = vm_map_phys(SELF, (void *)mr.mr_base, vram_size);
if(video_mem == MAP_FAILED)
panic("video_gr couldn't map video memory");
r.u.w.ax = SET_MODE; // VBE call, function 02 -- set VBE mode
r.u.w.bx = BIT(LINEAR_MODEL_BIT)|mode; // set bit 14: linear framebuffer
r.u.b.intno = BIOS_SERVICE;
if( sys_int86(&r) != OK ) {
printf("set_vbe_mode: sys_int86() failed \n");
return NULL;
}
switch(r.u.b.ah){
case 0x01:
printf("Function call failed \n");
return NULL;
break;
case 0x02:
printf("Function is not supported in current HW configuration \n");
return NULL;
break;
case 0x03:
printf("Function is invalid in current video mode \n");
return NULL;
break;
default:
break;
}
vram_phisical_address = info->PhysBasePtr;
return video_mem;
}
/*===========================================================================*
* hw_init *
*===========================================================================*/
static void hw_init(struct port *pp, int devind)
{
u8_t v8;
u16_t v16;
u32_t v32;
#if USE_INTS
int r, irq;
#endif
pp->p_devind= devind;
if (debug)
printf("hw_init: devind = %d\n", devind);
if (debug)
{
v16= pci_attr_r16(devind, PCI_CR);
printf("ti1225: command register 0x%x\n", v16);
}
v32= pci_attr_r32(devind, TI_CB_BASEADDR);
if (debug)
printf("ti1225: Cardbus/ExCA base address 0x%x\n", v32);
v32 &= PCI_BAR_MEM_MASK; /* Clear low order bits in base */
pp->csr_ptr=
(struct csr *) vm_map_phys(SELF, (void *) v32, I386_PAGE_SIZE);
if (pp->csr_ptr == MAP_FAILED)
panic("hw_init: vm_map_phys failed");
if (debug)
{
v8= pci_attr_r8(devind, TI_PCI_BUS_NR);
printf("ti1225: PCI bus number %d\n", v8);
}
v8= pci_attr_r8(devind, TI_CB_BUS_NR);
pp->p_cb_busnr= v8;
if (debug)
{
printf("ti1225: CardBus bus number %d\n", v8);
v8= pci_attr_r8(devind, TI_SO_BUS_NR);
printf("ti1225: Subordinate bus number %d\n", v8);
}
#if USE_INTS
irq= pci_attr_r8(devind, PCI_ILR);
pp->p_irq= irq;
printf("ti1225 using IRQ %d\n", irq);
#endif
v32= pci_attr_r32(devind, TI_LEGACY_BA);
v32 &= ~1;
if (debug)
{
printf("ti1225: PC Card 16-bit legacy-mode base address 0x%x\n",
v32);
}
if (v32 == 0)
panic("bad legacy-mode base address: %d", v32);
pp->p_exca_port= v32;
if (debug)
{
v32= pci_attr_r32(devind, TI_MF_ROUTE);
printf("ti1225: Multifunction routing 0x%08x\n", v32);
}
#if USE_INTS
pp->p_hook = pp->p_irq;
r= sys_irqsetpolicy(pp->p_irq, 0, &pp->p_hook);
if (r != OK)
panic("sys_irqsetpolicy failed: %d", r);
#endif
/* Clear CBB_BC_INTEXCA */
v16= pci_attr_r16(devind, CBB_BRIDGECTRL);
if (debug)
printf("ti1225: Bridge control 0x%04x\n", v16);
v16 &= ~CBB_BC_INTEXCA;
pci_attr_w16(devind, CBB_BRIDGECTRL, v16);
if (debug)
{
v32= pci_attr_r32(devind, TI_SYSCTRL);
printf("ti1225: System Control Register 0x%08x\n", v32);
v8= pci_attr_r8(devind, TI_CARD_CTRL);
printf("ti1225: Card Control 0x%02x\n", v8);
v8= pci_attr_r8(devind, TI_DEV_CTRL);
printf("ti1225: Device Control 0x%02x\n", v8);
}
/* Enable socket interrupts */
pp->csr_ptr->csr_mask |= CM_PWRMASK | CM_CDMASK | CM_CSTSMASK;
do_int(pp);
#if USE_INTS
r= sys_irqenable(&pp->p_hook);
if (r != OK)
panic("unable enable interrupts: %d", r);
#endif
}
/*
* Find a matching device. Return TRUE on success.
*/
static int
e1000_probe(e1000_t * e, int skip)
{
int r, devind, ioflag;
u16_t vid, did, cr;
u32_t status;
u32_t base, size;
char *dname;
E1000_DEBUG(3, ("%s: probe()\n", e->name));
/* Initialize communication to the PCI driver. */
pci_init();
/* Attempt to iterate the PCI bus. Start at the beginning. */
if ((r = pci_first_dev(&devind, &vid, &did)) == 0)
return FALSE;
/* Loop devices on the PCI bus. */
while (skip--) {
E1000_DEBUG(3, ("%s: probe() devind %d vid 0x%x did 0x%x\n",
e->name, devind, vid, did));
if (!(r = pci_next_dev(&devind, &vid, &did)))
return FALSE;
}
/* We found a matching card. Set card-specific properties. */
e->eeprom_read = eeprom_eerd;
switch (did) {
case E1000_DEV_ID_ICH10_D_BM_LM:
case E1000_DEV_ID_ICH10_R_BM_LF:
e->eeprom_read = eeprom_ich;
break;
case E1000_DEV_ID_82540EM:
case E1000_DEV_ID_82545EM:
case E1000_DEV_ID_82540EP_LP:
e->eeprom_done_bit = (1 << 4);
e->eeprom_addr_off = 8;
break;
default:
e->eeprom_done_bit = (1 << 1);
e->eeprom_addr_off = 2;
break;
}
/* Inform the user about the new card. */
if (!(dname = pci_dev_name(vid, did)))
dname = "Intel Pro/1000 Gigabit Ethernet Card";
E1000_DEBUG(1, ("%s: %s (%04x/%04x) at %s\n",
e->name, dname, vid, did, pci_slot_name(devind)));
/* Reserve PCI resources found. */
pci_reserve(devind);
/* Read PCI configuration. */
e->irq = pci_attr_r8(devind, PCI_ILR);
if ((r = pci_get_bar(devind, PCI_BAR, &base, &size, &ioflag)) != OK)
panic("failed to get PCI BAR: %d", r);
if (ioflag)
panic("PCI BAR is not for memory");
if ((e->regs = vm_map_phys(SELF, (void *)base, size)) == MAP_FAILED)
panic("failed to map hardware registers from PCI");
/* Enable DMA bus mastering if necessary. */
cr = pci_attr_r16(devind, PCI_CR);
if (!(cr & PCI_CR_MAST_EN))
pci_attr_w16(devind, PCI_CR, cr | PCI_CR_MAST_EN);
/* Optionally map flash memory. */
e1000_map_flash(e, devind, did);
/* Output debug information. */
status = e1000_reg_read(e, E1000_REG_STATUS);
E1000_DEBUG(3, ("%s: MEM at %p, IRQ %d\n", e->name, e->regs, e->irq));
E1000_DEBUG(3, ("%s: link %s, %s duplex\n", e->name,
status & 3 ? "up" : "down", status & 1 ? "full" : "half"));
return TRUE;
}
/*
* Initialize the MMC controller given a certain
* instance. this driver only handles a single
* mmchs controller at a given time.
*/
int
mmchs_init(uint32_t instance)
{
uint32_t value;
value = 0;
struct minix_mem_range mr;
spin_t spin;
mr.mr_base = MMCHS1_REG_BASE;
mr.mr_limit = MMCHS1_REG_BASE + 0x400;
if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) {
panic("Unable to request permission to map memory");
}
/* Set the base address to use */
base_address =
(uint32_t) vm_map_phys(SELF, (void *) MMCHS1_REG_BASE, 0x400);
if (base_address == (uint32_t) MAP_FAILED)
panic("Unable to map MMC memory");
#ifdef DM37XX
base_address = (unsigned long) base_address - 0x100;
#endif
/* Soft reset of the controller. This section is documented in the TRM
*/
/* Write 1 to sysconfig[0] to trigger a reset */
set32(base_address + MMCHS_SD_SYSCONFIG, MMCHS_SD_SYSCONFIG_SOFTRESET,
MMCHS_SD_SYSCONFIG_SOFTRESET);
/* Read sysstatus to know when it's done */
spin_init(&spin, SANE_TIMEOUT);
while (!(read32(base_address + MMCHS_SD_SYSSTATUS)
& MMCHS_SD_SYSSTATUS_RESETDONE)) {
if (spin_check(&spin) == FALSE) {
mmc_log_warn(&log, "mmc init timeout\n");
return 1;
}
}
/* Set SD default capabilities */
set32(base_address + MMCHS_SD_CAPA, MMCHS_SD_CAPA_VS_MASK,
MMCHS_SD_CAPA_VS18 | MMCHS_SD_CAPA_VS30);
/* TRM mentions MMCHS_SD_CUR_CAPA but does not describe how to limit
* the current */
uint32_t mask =
MMCHS_SD_SYSCONFIG_AUTOIDLE | MMCHS_SD_SYSCONFIG_ENAWAKEUP |
MMCHS_SD_SYSCONFIG_STANDBYMODE | MMCHS_SD_SYSCONFIG_CLOCKACTIVITY |
MMCHS_SD_SYSCONFIG_SIDLEMODE;
/* Automatic clock gating strategy */
value = MMCHS_SD_SYSCONFIG_AUTOIDLE_EN;
/* Enable wake-up capability */
value |= MMCHS_SD_SYSCONFIG_ENAWAKEUP_EN;
/* Smart-idle */
value |= MMCHS_SD_SYSCONFIG_SIDLEMODE_IDLE;
/* Both the interface and functional can be switched off */
value |= MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_OFF;
/* Go into wake-up mode when possible */
value |= MMCHS_SD_SYSCONFIG_STANDBYMODE_WAKEUP_INTERNAL;
/*
* wake-up configuration
*/
set32(base_address + MMCHS_SD_SYSCONFIG, mask, value);
/* Wake-up on sd interrupt for SDIO */
set32(base_address + MMCHS_SD_HCTL, MMCHS_SD_HCTL_IWE,
MMCHS_SD_HCTL_IWE_EN);
/*
* MMC host and bus configuration
*/
/* Configure data and command transfer (1 bit mode) */
set32(base_address + MMCHS_SD_CON, MMCHS_SD_CON_DW8,
MMCHS_SD_CON_DW8_1BIT);
set32(base_address + MMCHS_SD_HCTL, MMCHS_SD_HCTL_DTW,
MMCHS_SD_HCTL_DTW_1BIT);
/* Configure card voltage to 3.0 volt */
set32(base_address + MMCHS_SD_HCTL, MMCHS_SD_HCTL_SDVS,
MMCHS_SD_HCTL_SDVS_VS30);
/* Power on the host controller and wait for the
* MMCHS_SD_HCTL_SDBP_POWER_ON to be set */
set32(base_address + MMCHS_SD_HCTL, MMCHS_SD_HCTL_SDBP,
MMCHS_SD_HCTL_SDBP_ON);
// /* TODO: Add padconf/pinmux stuff here as documented in the TRM */
spin_init(&spin, SANE_TIMEOUT);
while ((read32(base_address + MMCHS_SD_HCTL) & MMCHS_SD_HCTL_SDBP)
!= MMCHS_SD_HCTL_SDBP_ON) {
if (spin_check(&spin) == FALSE) {
mmc_log_warn(&log, "mmc init timeout SDBP not set\n");
return 1;
}
}
/* Enable internal clock and clock to the card */
set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_ICE,
MMCHS_SD_SYSCTL_ICE_EN);
// @TODO Fix external clock enable , this one is very slow
// but we first need faster context switching
// set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_CLKD,
// (0x20 << 6));
set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_CLKD,
(0x5 << 6));
set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_CEN,
MMCHS_SD_SYSCTL_CEN_EN);
spin_init(&spin, SANE_TIMEOUT);
while ((read32(base_address + MMCHS_SD_SYSCTL) & MMCHS_SD_SYSCTL_ICS)
!= MMCHS_SD_SYSCTL_ICS_STABLE) {
if (spin_check(&spin) == FALSE) {
mmc_log_warn(&log, "clock not stable\n");
return 1;
}
}
/*
* See spruh73e page 3576 Card Detection, Identification, and Selection
*/
/* Enable command interrupt */
set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_CC_ENABLE,
MMCHS_SD_IE_CC_ENABLE_ENABLE);
/* Enable transfer complete interrupt */
set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_TC_ENABLE,
MMCHS_SD_IE_TC_ENABLE_ENABLE);
/* enable error interrupts */
/* NOTE: We are currently skipping the BADA interrupt it does get
* raised for unknown reasons */
set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_ERROR_MASK, 0x0fffffffu);
/* clear the error interrupts */
set32(base_address + MMCHS_SD_STAT, MMCHS_SD_STAT_ERROR_MASK,
0xffffffffu);
/* send a init signal to the host controller. This does not actually
* send a command to a card manner */
set32(base_address + MMCHS_SD_CON, MMCHS_SD_CON_INIT,
MMCHS_SD_CON_INIT_INIT);
/* command 0 , type other commands not response etc) */
write32(base_address + MMCHS_SD_CMD, 0x00);
spin_init(&spin, SANE_TIMEOUT);
while ((read32(base_address + MMCHS_SD_STAT) & MMCHS_SD_STAT_CC)
!= MMCHS_SD_STAT_CC_RAISED) {
if (read32(base_address + MMCHS_SD_STAT) & 0x8000) {
mmc_log_warn(&log, "%s, error stat %x\n",
__FUNCTION__,
read32(base_address + MMCHS_SD_STAT));
return 1;
}
if (spin_check(&spin) == FALSE) {
mmc_log_warn(&log,
"Interrupt not raised during init\n");
return 1;
}
}
/* clear the cc interrupt status */
set32(base_address + MMCHS_SD_STAT, MMCHS_SD_IE_CC_ENABLE,
MMCHS_SD_IE_CC_ENABLE_ENABLE);
/*
* Set Set SD_CON[1] INIT bit to 0x0 to end the initialization sequence
*/
set32(base_address + MMCHS_SD_CON, MMCHS_SD_CON_INIT,
MMCHS_SD_CON_INIT_NOINIT);
/* Set timeout */
set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_DTO,
MMCHS_SD_SYSCTL_DTO_2POW27);
/* Clean the MMCHS_SD_STAT register */
write32(base_address + MMCHS_SD_STAT, 0xffffffffu);
#ifdef USE_INTR
hook_id = 1;
if (sys_irqsetpolicy(OMAP3_MMC1_IRQ, 0, &hook_id) != OK) {
printf("mmc: couldn't set IRQ policy %d\n", OMAP3_MMC1_IRQ);
return 1;
}
/* enable signaling from MMC controller towards interrupt controller */
write32(base_address + MMCHS_SD_ISE, 0xffffffffu);
#endif
return 0;
}
