void uart_lowlevel_init(virtual_addr_t base, u32 reg_align, u32 baudrate, u32 input_clock) { u16 bdiv; bdiv = udiv32(input_clock, (16 * baudrate)); /* set DLAB bit */ vmm_out_8((u8 *)REG_UART_LCR(base,reg_align), 0x80); /* set baudrate divisor */ vmm_out_8((u8 *)REG_UART_DLL(base,reg_align), bdiv & 0xFF); /* set baudrate divisor */ vmm_out_8((u8 *)REG_UART_DLM(base,reg_align), (bdiv >> 8) & 0xFF); /* clear DLAB; set 8 bits, no parity */ vmm_out_8((u8 *)REG_UART_LCR(base,reg_align), 0x03); /* disable FIFO */ vmm_out_8((u8 *)REG_UART_FCR(base,reg_align), 0x01); /* no modem control DTR RTS */ vmm_out_8((u8 *)REG_UART_MCR(base,reg_align), 0x00); /* clear line status */ vmm_in_8((u8 *)REG_UART_LSR(base,reg_align)); /* read receive buffer */ vmm_in_8((u8 *)REG_UART_RBR(base,reg_align)); /* set scratchpad */ vmm_out_8((u8 *)REG_UART_SCR(base,reg_align), 0x00); /* set interrupt enable reg */ vmm_out_8((u8 *)REG_UART_IER(base,reg_align), 0x0F); }
bool uart_lowlevel_can_putc(virtual_addr_t base, u32 reg_align) { if (vmm_in_8((u8 *)REG_UART_LSR(base,reg_align)) & UART_LSR_THRE) { return TRUE; } return FALSE; }
u8 samsung_lowlevel_getc(virtual_addr_t base) { u8 data; /* Wait until there is data in the FIFO */ while (!samsung_lowlevel_can_getc(base)) ; data = vmm_in_8((void *)(base + S3C2410_URXH)); return data; }
u8 uart_lowlevel_getc(virtual_addr_t base, u32 reg_align) { while (!uart_lowlevel_can_getc(base, reg_align)); return (vmm_in_8((u8 *)REG_UART_RBR(base,reg_align))); }