int sil902x_CP_get_KSV(void)
{
char temp;
int KeyCount;
char KSV_Array[128];
do {
WriteByte(0xBC,0x1);
WriteByte(0xBD,0x25);
temp = ReadByte(0xBE);
} while( temp > 0x70 );
ReadModifyWrite(0x1A,0x6,0x6);
DBGMSG("[SIL902X] GetKSV()\n");
vpp_i2c_read(0x74,0x41,&temp,1);
KeyCount = (temp & 0x7F) * 5;
if (KeyCount != 0){
vpp_i2c_read(0x74,0x43,KSV_Array,KeyCount);
}
#if 1
{
int i;
DBGMSG("KeyCount = %d\n", (int) KeyCount);
for (i=0; i<KeyCount; i++){
DPRINT("KSV[%d] = %x\n", (int) i, (int) KSV_Array[i]);
}
}
#endif
temp = ReadByte(0x1A);
ReadModifyWrite(0x1A,0x8,0x0);
return 1;
}
int ad9389_get_edid(char *buf)
{
mdelay(50);
DBGMSG("get edid\n");
vpp_i2c_read(VPP_DVI_I2C_ID,0x7E, 0x0, buf, 128);
if( buf[0x7F] ){
vpp_i2c_read(VPP_DVI_I2C_ID,0x7E, 128, &buf[128], 128);
}
return 0;
}
static char ReadByte(unsigned int index)
{
unsigned char temp;
vpp_i2c_read(SIL902X_ADDR,index,&temp,1);
return temp;
}
void ve_ch7305_suspend(void){
int i;
for(i = 0; i < CH7305_REG_COUNT; i++)
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, i, ®s[i], 1);
}
int ad7393_init(void)
{
unsigned char buf[2];
buf[0] = 0xff;
vpp_i2c_read(AD7393_ADDR, 0x0, buf, 1);
if( (buf[0] == 0x0) || (buf[0] == 0xff) ){
return -1;
}
DPRINT("[AD7393] TV ext device\n");
return 0;
}
int ad9389_init(struct vout_s *vo)
{
unsigned char buf[2];
buf[0] = 0xff;
vpp_i2c_read(VPP_DVI_I2C_ID,0x72, 0xcf, buf, 1);
if( buf[0] != 0x70 ){
return -1;
}
DPRINT("[AD9389] HDMI ext device\n");
return 0;
}
int ad9389_init(void)
{
unsigned char buf[2];
buf[0] = 0xff;
vpp_i2c_read(0x72, 0xcf, buf, 1);
if( buf[0] != 0x70 ){
return -1;
}
DPRINT("[AD9389] HDMI ext device\n");
return 0;
}
void ad9389_set_power_down(int enable)
{
char reg;
vpp_i2c_read(VPP_DVI_I2C_ID,AD9389_ADDR,0x41,®,1);
if( enable ){
reg |= 0x40;
}
else {
reg &= ~0x40;
}
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR,0x41,®,1);
}
/*----------------------- Function Body --------------------------------------*/
int ad9389_check_plugin(int hotplug)
{
unsigned char buf[1];
int plugin;
unsigned int option[2];
vpp_i2c_read(VPP_DVI_I2C_ID,AD9389_ADDR,0x42,buf,1);
plugin = (buf[0] & BIT6)? 1:0;
printk("[AD9389] HDMI plug%s\n",(plugin)?"in":"out");
buf[0] = 0x80;
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR,0x94,buf,1); // enable INT
buf[0] = 0x80;
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR,0x96,buf,1); // clear HPD flag
vout_set_int_type(2); // GPIO0 3:rising edge, 2:falling edge
if( !hotplug ) return plugin;
option[0] = ad9389_colfmt;
option[1] = ad9389_dwidth;
option[1] |= (ad9389_spdif_enable)? 0x2:0x0;
if( plugin ){
do {
buf[0] = 0x10;
vpp_i2c_write(VPP_DVI_I2C_ID,AD9389_ADDR,0x41,buf,1);
vpp_i2c_read(VPP_DVI_I2C_ID,AD9389_ADDR,0x41,buf,1);
if((buf[0] & BIT6)==0) // Power up
break;
vpp_i2c_read(VPP_DVI_I2C_ID,AD9389_ADDR,0x42,buf,1);
plugin = (buf[0] & BIT6)? 1:0;
if( plugin == 0 )
return 0;
} while(1);
ad9389_set_mode(&option[0]);
}
return plugin;
}
void ve_ch7305_power_on()
{
// LVDS power on
reg_t reg63;
reg63.addr = 0x63;
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg63.addr, ®63.data, 1);
reg63.data &= ~0x40;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg63.addr, ®63.data, 1);
/* add for CH7305 PLL reset to prevent CH7305 from no signal ouput */
reg_t reg76;
reg76.addr = 0x76;
reg_t reg66;
reg66.addr = 0x66;
int timeout = 0;
int ret=0;
/* wait until CH7305 PLL is stable or timeout */
while( ((ret=vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg66.addr, ®66.data, 1))>0) && !(reg66.data & 0x04) && (timeout++)<3 )
{
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg76.addr, ®76.data, 1);
reg76.data &= ~0x04;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg76.addr, ®76.data, 1);
mdelay(100);
reg76.data |= 0x04;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg76.addr, ®76.data, 1);
mdelay(100);
}
// GPIO0 and GPIO1 control backlight and power
/*REG8_VAL(GPIO_BASE_ADDR+0x80) |= 0x03;
mdelay(10);
REG8_VAL(GPIO_BASE_ADDR+0xC0) |= 0x03;
mdelay(10);*/
}
/*the define and struct i2c_msg were declared int linux/i2c.h*/
int vt1632_check_plugin(int hotplug)
{
char buf[1];
int plugin;
if( vt1632_not_ready )
return 1;
vpp_i2c_read(VPP_DVI_I2C_ID,VT1632_ADDR,0x9,buf,1);
plugin = (buf[0]&0x4)? 1:0;
DPRINT("[VT1632] DVI plug%s\n",(plugin)?"in":"out");
vout_set_int_type(4);
return plugin;
}
/*the define and struct i2c_msg were declared int linux/i2c.h*/
int vt1632_check_plugin(void)
{
char buf[1];
int plugin;
if( vt1632_not_ready )
return 1;
buf[0] = 0;
vpp_i2c_read(VT1632_ADDR,0x9,buf,1);
plugin = (buf[0]&0x4)? 1:0;
DPRINT("[VT1632] DVI plug%s\n",(plugin)?"in":"out");
vppif_reg32_write((0xD8110000+0x300), 0x3<<(VPP_VOINT_NO*2),VPP_VOINT_NO*2,(plugin)?2:3); // GPIO0 3:rising edge, 2:falling edge
return plugin;
}
void ve_ch7305_power_off()
{
// GPIO0 and GPIO1 control backlight and power
/*REG8_VAL(GPIO_BASE_ADDR+0x80) &= ~0x03;
mdelay(10);
REG8_VAL(GPIO_BASE_ADDR+0xC0) &= ~0x03;
mdelay(10);*/
// LVDS power off
reg_t reg63;
reg63.addr = 0x63;
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg63.addr, ®63.data, 1);
reg63.data |= 0x40;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg63.addr, ®63.data,1);
}
// return: the read data
int cs8556_i2c_read(int addr)
{
#ifdef CONFIG_KERNEL
// return i2c_api_register_read(CS8556_ADDR, 2, addr);
char buf = 0;
vpp_i2c_read(CS8556_ID, CS8556_ADDR, addr, &buf, 1);
return buf;
#else
uchar data = 0;
i2c1_read(CS8556_ADDR, addr, 2, &data, 1);
return data;
#endif
}
/*--------------------End of Function Body -----------------------------------*/
int ad7393_check_plugin(int hotplug)
{
#if 1
return 1;
#else
char reg;
int plugin;
vpp_i2c_read(AD7393_ADDR,0x10,®,1);
plugin = (reg & 0x1)? 0:1; /* bit0: Y, bit1: C */
if( (reg & 0x02) == 0 ){
plugin |= 0x2;
}
printk("[AD7393] 0x%x, plug%s\n",reg,(plugin)?"in":"out");
return plugin;
#endif
}
int vt1632_init(struct vout_s *vo)
{
char buf[16];
vt1632_not_ready = 1;
vpp_i2c_read(VPP_DVI_I2C_ID,VT1632_ADDR, 0x0, buf, 2);
if( (buf[0] != 0x06) || (buf[1] != 0x11) ){ // check vender id
return -1;
}
vt1632_not_ready = 0;
buf[0x0] = 0x37;
buf[0x1] = 0x20;
vpp_i2c_write(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,2);
DPRINT("[VT1632] DVI ext device\n");
return 0;
}
void print_reg(){
reg_t reg;
int i,j;
DPRINT("********************************************\n");
DPRINT("[CH7305] Register:\n");
for(i = 0; i < 8; i++){
for(j = 0; j < 16; j++){
reg.addr = i*16 +j;
reg.data = 0xff;
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg.addr, ®.data, 1);
DPRINT("%x\t",reg.data);
}
DPRINT("\n");
}
DPRINT("*********************************************\n");
}
int vt1632_init(void)
{
char buf[16];
memset(buf, 0, 16);
vt1632_not_ready = 1;
vpp_i2c_read(VT1632_ADDR, 0x0, buf, 2);
if( (buf[0] != 0x06) || (buf[1] != 0x11) ){ // check vender id
DPRINT("vt1632 hw mode\n");
return -1;
}
vt1632_not_ready = 0;
buf[0x0] = 0x37;
buf[0x1] = 0x20;
vpp_i2c_write(VT1632_ADDR,0x8,buf,2);
return 0;
}
void vt1632_set_power_down(int enable)
{
char buf[1];
if( vt1632_not_ready )
return;
DBGMSG("vt1632_set_power_down(%d)\n",enable);
vpp_i2c_read(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,1);
if( enable ){
buf[0] &= ~BIT0;
}
else {
buf[0] |= BIT0;
}
vpp_i2c_write(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,1);
}
/*!
* \brief read EDID
*
* \retval None
*/
void sil902x_do_read_edid(int index,unsigned char *buf)
{
char int_bk;
char reg;
// DPRINT("[SIL902X] read edid\n");
WriteByte(0xC7,0x0); // access backdoor
WriteByte(0xBC,0x0); // program back door page 0
WriteByte(0xBD,0xF5);
WriteByte(0xBE,0x0); // prevent DDC NoACK lock the i2c
int_bk = ReadByte(0x3C);
WriteByte(0x3C,(int_bk & 0xFE)); // disable HPD & RSEN
reg = ReadByte(0x1A);
WriteByte(0x1A,(reg | 0x4)); // request DDC access
mdelay(1);
WriteByte(0x1A,(reg | 0x6)); // lock i2c bypass to DDC
mdelay(1);
if( index < 0x100 ){
vpp_i2c_read(0xA0,index,buf,128);
}
else {
vpp_i2c_enhanced_ddc_read(0xA0,index-0x100,buf,128);
}
WriteByte(0x1A,(reg & 0xF9)); // clear "request DDC access" bit, stop i2c bypass to DDC, switch i2c to 902x regs bank
while((ReadByte(0x1A) & 0x6) != 0 ){
int cnt = 0;
if( cnt > 10000 ){
DPRINT("[SIL902X] wait switch i2c\n");
}
} // wait switch i2c to 902x regs bank
WriteByte(0x3C,int_bk);
}
int ve_ch7305_init()
{
#ifdef CONFIG_PWM0_GPIO_Output_Without_Frequency_Control
/* Disable PWM0 frequency output to avoid CH7305 I20 hang situation */
PWM0_GPIO_Output_Without_Frequecny_Control(1);
#endif
reg_t id = {0x4A, 0xFF};
vpp_i2c_release();
vpp_i2c_init(CH7305_I2C_ID, CH7305_ADDR);
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, id.addr, &id.data, 1);
// CH7305 version ID is 0x81
if( id.data!= CH7305_ID){
DPRINT("[CH7305] Err: Fail to detect\n");
return -1;
}
DPRINT("[CH7305] Succeed to detect\n");
return 0;
}
int vt1632_set_mode(unsigned int *option)
{
char buf[1];
vpp_datawidht_t dwidth;
if( vt1632_not_ready )
return -1;
dwidth = option[1] & BIT0;
DBGMSG("vt1632_set_mode(%d)\n",(dwidth)?24:12);
vpp_i2c_read(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,1);
if( dwidth == VPP_DATAWIDHT_12 ){
buf[0] &= ~BIT2;
buf[0] |= BIT3;
}
else {
buf[0] |= BIT2;
buf[0] &= ~BIT3;
}
vpp_i2c_write(VPP_DVI_I2C_ID,VT1632_ADDR,0x8,buf,1);
return 0;
}
int ve_ch7305_set_mode(lcd_setting_t mode)
{
/* Channel and mods:
* Single channel: 800x600, 1024x768
* dual channel: 1280x1024, 1400x1050, 1600x1200
*/
reg_t pll_single[] = {
{0x6F, 0x00},
{0x70, 0x40},
{0x71, 0xED},
{0x72, 0xA3},
{0x73, 0xC8},
{0x74, 0xF6},
{0x75, 0x00},
{0x76, 0xAD},
{0x77, 0x00},
{0x78, 0x80},
{0x79, 0x02},
{0x7A, 0x00},
{0x7B, 0x00},
{0x7C, 0x30},
{0x7D, 0x02},
{0x7E, 0x00},
{0x7F, 0x10}
};
reg_t pll_dual[] = {
{0x6F, 0x00},
{0x70, 0x40},
{0x71, 0xE3},
{0x72, 0xAD},
{0x73, 0xDB},
{0x74, 0xF6},
{0x75, 0x00},
{0x76, 0x8F},
{0x77, 0x00},
{0x78, 0x80},
{0x79, 0x02},
{0x7A, 0x00},
{0x7B, 0x00},
{0x7C, 0x30},
{0x7D, 0x02},
{0x7E, 0x00},
{0x7F, 0x10}
};
// Print registers' value
// print_reg();
int i;
for (i = 0; i < 17; i++ ){
if ( mode.panel_mode & DUAL_CHANNEL )
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, pll_dual[i].addr, &pll_dual[i].data, 1);
else
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, pll_single[i].addr, &pll_single[i].data, 1);
}
reg_t reg64;
reg64.addr = 0x64;
// Input data select
vpp_i2c_read(CH7305_I2C_ID, CH7305_ADDR, reg64.addr, ®64.data, 1);
if ( mode.panel_mode & DUAL_CHANNEL )
reg64.data |= 0x10;
else
reg64.data &= ~0x10;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg64.addr, ®64.data, 1);
//Power sequence
reg_t T1,T2, T3, T4, T5;
T1.addr =0x67;
T2.addr =0x68;
T3.addr =0x69;
T4.addr =0x6A;
T5.addr =0x6B;
T1.data = 0x31;
T2.data = 0x68;
T3.data = 0x68;
T4.data = 0x31;
T5.data = 0x4;
unsigned char val;
// T1(Power On Time)
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T1.addr, &T1.data, 1);
val = T2.data & 0x80;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T2.addr, &val, 1);
// T4(Power Off Time)
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T4.addr, &T4.data, 1);
val = T3.data & 0x80;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T3.addr, &val, 1);
// T5(Power Cycle Time)
val = T5.data & 0x3F;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T5.addr, &val, 1);
// T2(Black Light Enable Time)
val = T2.data & 0x7F;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T2.addr, &val, 1);
// T3(Black Light Disable Time)
val = T3.data & 0x7F;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, T3.addr, &val, 1);
// LVDS24
if ( mode.panel_mode & OUTPUT_24 )
reg64.data |= 0x20; // Output 24bits
else
reg64.data &= ~0x20; // Output 18bits
// Dithering
if ( mode.panel_mode & EN_DITHERING )
reg64.data &= ~0x08; // Enable dithering
else
reg64.data |= 0x08; // Disable dithering
// LDI
if ( mode.panel_mode & LDI)
reg64.data |= 0x1; // openLDI
else
reg64.data &= ~0x1; // SPWG
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg64.addr, ®64.data, 1);
// De-skew
reg_t reg1d;
reg1d.addr = 0x1d;
reg1d.data = 0x40;
reg1d.data |= mode.deskew_xcmd & 0xF;
vpp_i2c_write(CH7305_I2C_ID, CH7305_ADDR, reg1d.addr, ®1d.data, 1);
//print registers' value
print_reg();
return 0;
}
