void scl_suspend(int sts)
{
switch( sts ){
case 0: // disable module
vpp_mod_set_clock(VPP_MOD_SCL,VPP_FLAG_ENABLE,1);
scl_pm_enable = vppif_reg32_read(SCL_ALU_ENABLE);
vppif_reg32_write(SCL_ALU_ENABLE,0);
scl_pm_r_mif1 = vppif_reg32_read(SCLR_MIF_ENABLE);
scl_pm_r_mif2 = vppif_reg32_read(SCLR_MIF2_ENABLE);
vppif_reg32_write(SCLR_MIF_ENABLE,0);
vppif_reg32_write(SCLR_MIF2_ENABLE,0);
scl_pm_w_mif = vppif_reg32_read(SCLW_MIF_ENABLE);
vppif_reg32_write(SCLW_MIF_ENABLE,0);
break;
case 1: // disable tg
scl_pm_tg = vppif_reg32_read(SCL_TG_ENABLE);
vppif_reg32_write(SCL_TG_ENABLE,0);
break;
case 2: // backup register
p_scl->reg_bk = vpp_backup_reg(REG_SCL_BASE1_BEGIN,(REG_SCL_BASE1_END-REG_SCL_BASE1_BEGIN));
scl_pm_bk2 = vpp_backup_reg(REG_SCL_BASE2_BEGIN,(REG_SCL_BASE2_END-REG_SCL_BASE2_BEGIN));
break;
default:
break;
}
}
void govw_resume(int sts)
{
switch( sts ){
case 0: // restore register
vpp_restore_reg(REG_GOVW_BEGIN,(REG_GOVW_END-REG_GOVW_BEGIN),p_govw->reg_bk);
p_govw->reg_bk = 0;
break;
case 1: // enable module
vppif_reg32_write(GOVW_HD_MIF_ENABLE,govw_pm_enable);
break;
case 2: // enable tg
vppif_reg32_write(GOVW_TG_ENABLE,govw_pm_tg);
vpp_mod_set_clock(VPP_MOD_GOVW,VPP_FLAG_DISABLE,1);
break;
default:
break;
}
}
void govw_suspend(int sts)
{
switch( sts ){
case 0: // disable module
vpp_mod_set_clock(VPP_MOD_GOVW,VPP_FLAG_ENABLE,1);
govw_pm_tg = vppif_reg32_read(GOVW_TG_ENABLE);
vppif_reg32_write(GOVW_TG_ENABLE,0);
govw_pm_enable = vppif_reg32_read(GOVW_HD_MIF_ENABLE);
vppif_reg32_write(GOVW_HD_MIF_ENABLE,0);
break;
case 1: // disable tg
break;
case 2: // backup register
p_govw->reg_bk = vpp_backup_reg(REG_GOVW_BEGIN,(REG_GOVW_END-REG_GOVW_BEGIN));
break;
default:
break;
}
}
static void scl_proc_scale_complete_work(void)
#endif
{
// DPRINT("[SCL] scl_proc_scale_complete_work\n");
#ifndef WMT_FTBLK_VPU
scl_set_timing_master(VPP_MOD_GOVW);
p_vpu->fb_p->set_framebuf(&p_vpu->fb_p->fb);
g_vpp.govw_skip_frame = 1;
#endif
scl_scale_complete = 1;
#ifdef __KERNEL__
#ifdef CONFIG_SCL_DIRECT_PATH_DEBUG
{
extern void vpp_scl_fb_cal_tmr(int begin);
vpp_scl_fb_cal_tmr(0);
}
#endif
wake_up_interruptible(&scl_proc_scale_event);
#endif
vpp_mod_set_clock(VPP_MOD_SCL,VPP_FLAG_DISABLE,0);
}
void scl_resume(int sts)
{
switch( sts ){
case 0: // restore register
vpp_restore_reg(REG_SCL_BASE1_BEGIN,(REG_SCL_BASE1_END-REG_SCL_BASE1_BEGIN),p_scl->reg_bk);
vpp_restore_reg(REG_SCL_BASE2_BEGIN,(REG_SCL_BASE2_END-REG_SCL_BASE2_BEGIN),scl_pm_bk2);
p_scl->reg_bk = 0;
scl_pm_bk2 = 0;
break;
case 1: // enable module
vppif_reg32_write(SCLW_MIF_ENABLE,scl_pm_w_mif);
vppif_reg32_write(SCLR_MIF_ENABLE,scl_pm_r_mif1);
vppif_reg32_write(SCLR_MIF2_ENABLE,scl_pm_r_mif2);
vppif_reg32_write(SCL_ALU_ENABLE,scl_pm_enable);
break;
case 2: // enable tg
vppif_reg32_write(SCL_TG_ENABLE,scl_pm_tg);
vpp_mod_set_clock(VPP_MOD_SCL,VPP_FLAG_DISABLE,1);
break;
default:
break;
}
}
int scl_do_recursive_scale(vdo_framebuf_t *src_fb,vdo_framebuf_t *dst_fb)
{
int ret = 0;
vpp_filter_mode_t filter;
vpp_mod_set_clock(VPP_MOD_SCL,VPP_FLAG_ENABLE,0);
scl_set_timing_master(VPP_MOD_SCL);
filter = ( (src_fb->img_w == dst_fb->img_w) && (src_fb->img_h == dst_fb->img_h) )? p_scl->filter_mode:VPP_FILTER_SCALE;
scl_set_filter_mode(filter,1);
p_scl->fb_p->fb = *src_fb;
p_scl->fb_p->set_framebuf(src_fb);
#ifdef CONFIG_HW_SCL_SCALEDN_GARBAGE_EDGE
// The ¡§start address¡¨ and ¡§start address + Horizontal active size¡¨ have to be
// avoiding the following offset failed address offset : ( 34 , 36 , 38 ) + n*64
{
unsigned int beg,end;
unsigned int temp;
beg = dst_fb->y_addr;
end = dst_fb->y_addr + dst_fb->img_w - 1;
temp = beg % 64;
if( (temp >=34) && (temp <=38) ){
temp = 40 - temp;
dst_fb->y_addr += temp;
dst_fb->c_addr += temp * ((dst_fb->col_fmt==VDO_COL_FMT_YUV444)?2:1);
beg += temp;
}
temp = end % 64;
if( (temp >=34) && (temp <=38) ){
end -= (temp - 32);
dst_fb->img_w = end - beg;
}
}
#endif
p_sclw->fb_p->fb = *dst_fb;
p_sclw->fb_p->set_framebuf(dst_fb);
// scale process
scl_set_enable(VPP_FLAG_ENABLE);
sclr_set_mif_enable(VPP_FLAG_ENABLE);
if( filter != VPP_FILTER_SCALE )
sclr_set_mif2_enable(VPP_FLAG_ENABLE);
#if 1
// #ifdef SCL_ONESHOT_ENABLE
vppif_reg32_write(SCL_ONESHOT_ENABLE,1);
#endif
sclw_set_mif_enable(VPP_FLAG_ENABLE);
scl_set_tg_enable(VPP_FLAG_ENABLE);
#ifdef CONFIG_VPP_CHECK_SCL_STATUS
vppif_reg32_out(REG_SCL_TG_STS+0x0,BIT0);
vppif_reg32_out(REG_SCLW_FF_CTL,0x10101);
#endif
scl_scale_complete = 0;
vppm_set_int_enable(VPP_FLAG_ENABLE,SCL_COMPLETE_INT);
if( p_scl->scale_sync ){
vpp_irqproc_work(SCL_COMPLETE_INT,scl_proc_scale_complete,0,1);
scl_proc_scale_finish();
}
else {
vpp_irqproc_work(SCL_COMPLETE_INT,scl_proc_scale_complete,0,0);
}
return ret;
}