int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq = -1;
switch (slot) {
case 12:
vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN,
TRIGGER_LEVEL,
SIGNAL_THROUGH);
vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN,
LEVEL_LOW);
irq = TB0219_PCI_SLOT1_IRQ;
break;
case 13:
vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN,
TRIGGER_LEVEL,
SIGNAL_THROUGH);
vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN,
LEVEL_LOW);
irq = TB0219_PCI_SLOT2_IRQ;
break;
case 14:
vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN,
TRIGGER_LEVEL,
SIGNAL_THROUGH);
vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN,
LEVEL_LOW);
irq = TB0219_PCI_SLOT3_IRQ;
break;
default:
break;
}
return irq;
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq = -1;
switch (slot) {
case 12:
vr41xx_set_irq_trigger(GD82559_1_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW);
irq = GD82559_1_IRQ;
break;
case 13:
vr41xx_set_irq_trigger(GD82559_2_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(GD82559_2_PIN, IRQ_LEVEL_LOW);
irq = GD82559_2_IRQ;
break;
case 14:
switch (pin) {
case 1:
vr41xx_set_irq_trigger(UPD720100_INTA_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(UPD720100_INTA_PIN,
IRQ_LEVEL_LOW);
irq = UPD720100_INTA_IRQ;
break;
case 2:
vr41xx_set_irq_trigger(UPD720100_INTB_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(UPD720100_INTB_PIN,
IRQ_LEVEL_LOW);
irq = UPD720100_INTB_IRQ;
break;
case 3:
vr41xx_set_irq_trigger(UPD720100_INTC_PIN,
IRQ_TRIGGER_LEVEL,
IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(UPD720100_INTC_PIN,
IRQ_LEVEL_LOW);
irq = UPD720100_INTC_IRQ;
break;
default:
break;
}
break;
default:
break;
}
return irq;
}
void __init pcibios_fixup_irqs(void)
{
struct pci_dev *dev;
u8 slot, pin;
pci_for_each_dev(dev) {
slot = PCI_SLOT(dev->devfn);
dev->irq = 0;
switch (slot) {
case 12:
vr41xx_set_irq_trigger(GD82559_1_PIN, TRIGGER_LEVEL,
SIGNAL_THROUGH);
vr41xx_set_irq_level(GD82559_1_PIN, LEVEL_LOW);
dev->irq = GD82559_1_IRQ;
break;
case 13:
vr41xx_set_irq_trigger(GD82559_2_PIN, TRIGGER_LEVEL,
SIGNAL_THROUGH);
vr41xx_set_irq_level(GD82559_2_PIN, LEVEL_LOW);
dev->irq = GD82559_2_IRQ;
break;
case 14:
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
switch (pin) {
case 1:
vr41xx_set_irq_trigger(UPD720100_INTA_PIN,
TRIGGER_LEVEL,
SIGNAL_THROUGH);
vr41xx_set_irq_level(UPD720100_INTA_PIN, LEVEL_LOW);
dev->irq = UPD720100_INTA_IRQ;
break;
case 2:
vr41xx_set_irq_trigger(UPD720100_INTB_PIN,
TRIGGER_LEVEL,
SIGNAL_THROUGH);
vr41xx_set_irq_level(UPD720100_INTB_PIN, LEVEL_LOW);
dev->irq = UPD720100_INTB_IRQ;
break;
case 3:
vr41xx_set_irq_trigger(UPD720100_INTC_PIN,
TRIGGER_LEVEL,
SIGNAL_THROUGH);
vr41xx_set_irq_level(UPD720100_INTC_PIN, LEVEL_LOW);
dev->irq = UPD720100_INTC_IRQ;
break;
}
break;
}
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
}
static void tb0219_pci_irq_init(void)
{
/* PCI Slot 1 */
vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN, IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN, IRQ_LEVEL_LOW);
/* PCI Slot 2 */
vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN, IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN, IRQ_LEVEL_LOW);
/* PCI Slot 3 */
vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN, IRQ_TRIGGER_LEVEL, IRQ_SIGNAL_THROUGH);
vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN, IRQ_LEVEL_LOW);
}
static inline void vrc4173_icu_init(int cascade_irq)
{
int i;
if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15))
return;
vrc4173_outw(0, VRC4173_MSYSINT1REG);
vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH);
vr41xx_set_irq_level(GIU_IRQ_TO_PIN(cascade_irq), LEVEL_LOW);
for (i = VRC4173_IRQ_BASE; i <= VRC4173_IRQ_LAST; i++)
irq_desc[i].handler = &vrc4173_irq_type;
}
void __init rockhopper_init_irq(void)
{
int i;
if(!vr4133_rockhopper) {
printk(KERN_ERR "Not a Rockhopper Board \n");
return;
}
for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
irq_desc[i].chip = &i8259_irq_type;
setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH);
vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH);
vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number);
}