static int
pmac_ide_do_setfeature(ide_drive_t *drive, byte command)
{
unsigned long flags;
byte old_select;
int result = 1;
save_flags(flags);
cli();
old_select = IN_BYTE(IDE_SELECT_REG);
OUT_BYTE(drive->select.all, IDE_SELECT_REG);
udelay(10);
OUT_BYTE(IDE_SETXFER, IDE_FEATURE_REG);
OUT_BYTE(command, IDE_NSECTOR_REG);
if(wait_for_ready(drive)) {
printk("pmac_ide_do_setfeature disk not ready before SET_FEATURE!\n");
goto out;
}
OUT_BYTE(IDE_SETFEATURE, IDE_COMMAND_REG);
result = wait_for_ready(drive);
if (result)
printk("pmac_ide_do_setfeature disk not ready after SET_FEATURE !\n");
out:
OUT_BYTE(old_select, IDE_SELECT_REG);
restore_flags(flags);
return result;
}
/* Note: We don't use the generic routine here because some of Apple's
* controller seem to be very sensitive about how things are done.
* We should probably set the NIEN bit, but that's an example of thing
* that can cause the controller to hang under some circumstances when
* done on the media-bay CD-ROM during boot. We do get occasional
* spurrious interrupts because of that.
* --BenH
*/
static int
pmac_ide_do_setfeature(ide_drive_t *drive, byte command)
{
unsigned long flags;
int result = 1;
save_flags(flags);
cli();
udelay(1);
SELECT_DRIVE(HWIF(drive), drive);
SELECT_MASK(HWIF(drive), drive, 0);
udelay(1);
if(wait_for_ready(drive)) {
printk(KERN_ERR "pmac_ide_do_setfeature disk not ready before SET_FEATURE!\n");
goto out;
}
OUT_BYTE(SETFEATURES_XFER, IDE_FEATURE_REG);
OUT_BYTE(command, IDE_NSECTOR_REG);
OUT_BYTE(WIN_SETFEATURES, IDE_COMMAND_REG);
udelay(1);
result = wait_for_ready(drive);
if (result)
printk(KERN_ERR "pmac_ide_do_setfeature disk not ready after SET_FEATURE !\n");
out:
restore_flags(flags);
return result;
}
static int wait_for_nand_bank_ready(int bank)
{
u32 toTest;
u64 startTime;
writel(((WEHighHoldTime & FMCTRL_TWH_MASK) << FMCTRL_TWH_SHIFT) | ((WPPulseTime & FMCTRL_TWP_MASK) << FMCTRL_TWP_SHIFT)
| (1 << (banksTable[bank] + 1)) | FMCTRL0_ON | FMCTRL0_WPB, NAND + FMCTRL0);
toTest = 1 << (bank + 4);
if((readl(NAND + FMCSTAT) & toTest) != 0)
{
writel(toTest, NAND + FMCSTAT);
}
writel(FMCTRL1_FLUSHFIFOS, NAND + FMCTRL1);
writel(NAND_CMD_READSTATUS, NAND + NAND_CMD);
wait_for_ready(500);
startTime = iphone_microtime();
while(true)
{
u32 data;
writel(0, NAND + FMDNUM);
writel(FMCTRL1_DOREADDATA, NAND + FMCTRL1);
if(wait_for_transfer_done(500) != 0)
{
LOG("nand: wait_for_nand_bank_ready: wait for transfer done timed out\n");
return -ETIMEDOUT;
}
data = readl(NAND + FMFIFO);
writel(FMCTRL1_FLUSHRXFIFO, NAND + FMCTRL1);
if((data & (1 << 6)) == 0)
{
if(iphone_has_elapsed(startTime, 500 * 1000))
{
LOG("nand: wait_for_nand_bank_ready: wait for bit 6 of DMA timed out\n");
return -ETIMEDOUT;
}
} else
{
break;
}
}
writel(0, NAND + NAND_CMD);
wait_for_ready(500);
#ifdef FTL_PROFILE
if(InWrite) Time_wait_for_nand_bank_ready += iphone_microtime() - startTime;
#endif
return 0;
}
DRESULT dataflash_random_read(BYTE *buff, DWORD offset, DWORD length) {
if (!length) return RES_PARERR;
if (status & STA_NOINIT) return RES_NOTRDY;
if (offset+length > MAX_PAGE*256) return RES_PARERR;
do {
wait_for_ready();
DWORD pageaddr = ((offset/256) << 9) | (offset%256);
DWORD remaining = 256 - offset%256;
if (remaining > length) {
remaining = length;
}
length -= remaining;
offset += remaining;
CS_LOW();
xmit_spi(OP_PAGEREAD);
xmit_spi((BYTE)(pageaddr >> 16));
xmit_spi((BYTE)(pageaddr >> 8));
xmit_spi((BYTE)pageaddr);
xmit_spi(0x00); // follow up with 4 don't care bytes
xmit_spi(0x00);
xmit_spi(0x00);
xmit_spi(0x00);
do {
rcvr_spi_m(buff++);
} while (--remaining);
CS_HIGH();
} while (length);
return length ? RES_ERROR : RES_OK;
}
static int igt_wakeup_thread(void *arg)
{
struct igt_wakeup *w = arg;
struct intel_wait wait;
while (wait_for_ready(w)) {
GEM_BUG_ON(kthread_should_stop());
intel_wait_init_for_seqno(&wait, w->seqno);
intel_engine_add_wait(w->engine, &wait);
for (;;) {
set_current_state(TASK_UNINTERRUPTIBLE);
if (i915_seqno_passed(intel_engine_get_seqno(w->engine),
w->seqno))
break;
if (test_bit(STOP, &w->flags)) /* emergency escape */
break;
schedule();
}
intel_engine_remove_wait(w->engine, &wait);
__set_current_state(TASK_RUNNING);
}
return 0;
}
int cmd_spi_rx(spi_t *spi,char *data, size_t max_len, int timeout_ms)
{
int i;
/* wait for ready from client */
int size;
int result = wait_for_ready(spi, timeout_ms, &size);
if(result < 0) {
return result;
}
/* nothing to read */
if(size == 0) {
return 0;
}
/* send RX data command */
buffer[0] = CMD_RX;
buffer[1] = (char)(size);
result = spi_transmit(spi,NULL,buffer,2);
if(result < 0) {
return result;
}
/* receive data */
result = spi_transmit(spi,data,NULL,size);
if(result < 0) {
return result;
}
return size;
}
int nand_read(int bank, int page, u8* buffer, u8* spare, bool doECC, bool checkBlank)
{
bool eccFailed;
if(bank >= Geometry.banksTotal)
return -EINVAL;
if(page >= Geometry.pagesPerBank)
return -EINVAL;
if(buffer == NULL && spare == NULL)
return -EINVAL;
#ifdef FTL_PROFILE
InWrite = true;
#endif
writel(((WEHighHoldTime & FMCTRL_TWH_MASK) << FMCTRL_TWH_SHIFT) | ((WPPulseTime & FMCTRL_TWP_MASK) << FMCTRL_TWP_SHIFT)
| (1 << (banksTable[bank] + 1)) | FMCTRL0_ON | FMCTRL0_WPB, NAND + FMCTRL0);
writel(0, NAND + NAND_CMD);
if(wait_for_ready(500) != 0) {
LOG("nand: bank setting failed\n");
goto FIL_read_error;
}
writel(FMANUM_TRANSFERSETTING, NAND + FMANUM);
if(buffer) {
writel(page << 16, NAND + FMADDR0); // lower bits of the page number to the upper bits of CONFIG3
writel((page >> 16) & 0xFF, NAND + FMADDR1); // upper bits of the page number
} else {
int nand_read(int bank, int page, uint8_t* buffer, uint8_t* spare, int doECC, int checkBlank) {
if(bank >= Geometry.banksTotal)
return ERROR_ARG;
if(page >= Geometry.pagesPerBank)
return ERROR_ARG;
if(buffer == NULL && spare == NULL)
return ERROR_ARG;
SET_REG(NAND + FMCTRL0,
((WEHighHoldTime & FMCTRL_TWH_MASK) << FMCTRL_TWH_SHIFT) | ((WPPulseTime & FMCTRL_TWP_MASK) << FMCTRL_TWP_SHIFT)
| (1 << (banksTable[bank] + 1)) | FMCTRL0_ON | FMCTRL0_WPB);
SET_REG(NAND + NAND_CMD, 0);
if(wait_for_ready(500) != 0) {
bufferPrintf("nand: bank setting failed\r\n");
goto FIL_read_error;
}
SET_REG(NAND + FMANUM, FMANUM_TRANSFERSETTING);
if(buffer) {
SET_REG(NAND + FMADDR0, page << 16); // lower bits of the page number to the upper bits of CONFIG3
SET_REG(NAND + FMADDR1, (page >> 16) & 0xFF); // upper bits of the page number
} else {
int nand_read(int bank, int page, uint8_t* buffer, uint8_t* spare, int doECC, int checkBlank) {
if(bank >= Data.banksTotal)
return ERROR_ARG;
if(page >= Data.pagesPerBank)
return ERROR_ARG;
if(buffer == NULL && spare == NULL)
return ERROR_ARG;
SET_REG(NAND + NAND_CONFIG,
((NANDSetting1 & NAND_CONFIG_SETTING1MASK) << NAND_CONFIG_SETTING1SHIFT) | ((NANDSetting2 & NAND_CONFIG_SETTING2MASK) << NAND_CONFIG_SETTING2SHIFT)
| (1 << (banksTable[bank] + 1)) | NAND_CONFIG_DEFAULTS);
SET_REG(NAND + NAND_CMD, 0);
if(wait_for_ready(500) != 0) {
bufferPrintf("nand: bank setting failed\r\n");
goto FIL_read_error;
}
SET_REG(NAND + NAND_CONFIG4, NAND_CONFIG4_TRANSFERSETTING);
if(buffer) {
SET_REG(NAND + NAND_CONFIG3, page << 16); // lower bits of the page number to the upper bits of CONFIG3
SET_REG(NAND + NAND_CONFIG5, (page >> 16) & 0xFF); // upper bits of the page number
} else {
void bs_hw_done()//bool dealloc
{
if ( !(broadsheet_ignore_hw_ready() || broadsheet_force_hw_not_ready()) )
{
// Wait until any pending operations are done before shutting down.
//
einkfb_debug("Waiting for HRDY before shutting down...\n");
wait_for_ready();
}
#ifdef MXC31
#ifdef CONFIG_MACH_MX31ADS
// Reset the level translator for the two GPIO inputs (HIRQ and HRDY)
pin_addr = PBC_BCTRL2_LDCIO_EN;
__raw_writew(pin_addr, PBC_BASE_ADDRESS + PBC_BCTRL2_CLEAR);
mdelay(100); // Pause 100 ms to allow level translator to settle
#elif CONFIG_MACH_MARIO_MX
mxc_free_gpio(BROADSHEET_RST_LINE);
#endif
#ifdef USE_BS_IRQ
disable_irq(BROADSHEET_HIRQ_IRQ);
free_irq(BROADSHEET_HIRQ_IRQ, NULL);
#endif
mxc_free_gpio(BROADSHEET_HIRQ_LINE);
mxc_free_gpio(BROADSHEET_HRDY_LINE);
#endif
einkfb_debug("Released Broadsheet GPIO pins and IRQs\n");
}
static void codec_init(struct device *dev, u32 base, int addr)
{
u32 reg32;
const u32 *verb;
u32 verb_size;
int i;
printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
/* 1 */
if (wait_for_ready(base) == -1) {
printk(BIOS_DEBUG, " codec not ready.\n");
return;
}
reg32 = (addr << 28) | 0x000f0000;
write32(base + 0x60, reg32);
if (wait_for_valid(base) == -1) {
printk(BIOS_DEBUG, " codec not valid.\n");
return;
}
reg32 = read32(base + 0x64);
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
verb_size = find_verb(dev, reg32, &verb);
if (!verb_size) {
printk(BIOS_DEBUG, "Azalia: No verb!\n");
return;
}
printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
/* 3 */
for (i = 0; i < verb_size; i++) {
if (wait_for_ready(base) == -1)
return;
write32(base + 0x60, verb[i]);
if (wait_for_valid(base) == -1)
return;
}
printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
}
void command( int v )
{
wait_for_ready();
gpio_hdc( 0 );
gpio_hcs_l( 0 );
gpio_hwe_l( 0 );
wr_gpio_hdb( v );
gpio_hwe_l( 1 );
gpio_hcs_l( 1 );
}
bool gsm_on()
{
gsm_on_raw();
if ( !wait_for_response( "+PSSUP", 0 ) || !wait_for_ready() )
{
gsm_off();
return false;
}
return true;
}
static void codec_init(void *base, int addr)
{
u32 dword;
u32 *verb;
u32 verb_size;
int i;
/* 1 */
if (wait_for_ready(base) == -1)
return;
dword = (addr << 28) | 0x000f0000;
write32(base + 0x60, dword);
if (wait_for_valid(base) == -1)
return;
dword = read32(base + 0x64);
/* 2 */
printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
verb_size = find_verb(dword, &verb);
if (!verb_size) {
printk(BIOS_DEBUG, "No verb!\n");
return;
}
printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
/* 3 */
for (i = 0; i < verb_size; i++) {
if (wait_for_ready(base) == -1)
return;
write32(base + 0x60, verb[i]);
if (wait_for_valid(base) == -1)
return;
}
printk(BIOS_DEBUG, "verb loaded!\n");
}
static int bank_setup(int bank) {
SET_REG(NAND + NAND_CONFIG,
((NANDSetting1 & NAND_CONFIG_SETTING1MASK) << NAND_CONFIG_SETTING1SHIFT) | ((NANDSetting2 & NAND_CONFIG_SETTING2MASK) << NAND_CONFIG_SETTING2SHIFT)
| (1 << (banksTable[bank] + 1)) | NAND_CONFIG_DEFAULTS);
uint32_t toTest = 1 << (bank + 4);
if((GET_REG(NAND + NAND_STATUS) & toTest) != 0) {
SET_REG(NAND + NAND_STATUS, toTest);
}
SET_REG(NAND + NAND_CON, NAND_CON_SETTING1);
SET_REG(NAND + NAND_CMD, NAND_CMD_READSTATUS);
wait_for_ready(500);
uint64_t startTime = timer_get_system_microtime();
while(TRUE) {
SET_REG(NAND + NAND_TRANSFERSIZE, 0);
SET_REG(NAND + NAND_CON, NAND_CON_BEGINTRANSFER);
if(wait_for_status_bit_3(500) != 0) {
bufferPrintf("nand: bank_setup: wait for status bit 3 timed out\r\n");
return ERROR_TIMEOUT;
}
uint32_t data = GET_REG(NAND + NAND_DMA_SOURCE);
SET_REG(NAND + NAND_CON, NAND_CON_SETTING2);
if((data & (1 << 6)) == 0) {
if(has_elapsed(startTime, 500 * 1000)) {
bufferPrintf("nand: bank_setup: wait for bit 6 of DMA timed out\r\n");
return ERROR_TIMEOUT;
}
} else {
break;
}
}
SET_REG(NAND + NAND_CMD, 0);
wait_for_ready(500);
return 0;
}
static int wait_for_nand_bank_ready(int bank) {
SET_REG(NAND + FMCTRL0,
((WEHighHoldTime & FMCTRL_TWH_MASK) << FMCTRL_TWH_SHIFT) | ((WPPulseTime & FMCTRL_TWP_MASK) << FMCTRL_TWP_SHIFT)
| (1 << (banksTable[bank] + 1)) | FMCTRL0_ON | FMCTRL0_WPB);
uint32_t toTest = 1 << (bank + 4);
if((GET_REG(NAND + FMCSTAT) & toTest) != 0) {
SET_REG(NAND + FMCSTAT, toTest);
}
SET_REG(NAND + FMCTRL1, FMCTRL1_FLUSHFIFOS);
SET_REG(NAND + NAND_CMD, NAND_CMD_READSTATUS);
wait_for_ready(500);
uint64_t startTime = timer_get_system_microtime();
while(TRUE) {
SET_REG(NAND + FMDNUM, 0);
SET_REG(NAND + FMCTRL1, FMCTRL1_DOREADDATA);
if(wait_for_transfer_done(500) != 0) {
bufferPrintf("nand: wait_for_nand_bank_ready: wait for transfer done timed out\r\n");
return ERROR_TIMEOUT;
}
uint32_t data = GET_REG(NAND + FMFIFO);
SET_REG(NAND + FMCTRL1, FMCTRL1_FLUSHRXFIFO);
if((data & (1 << 6)) == 0) {
if(has_elapsed(startTime, 500 * 1000)) {
bufferPrintf("nand: wait_for_nand_bank_ready: wait for bit 6 of DMA timed out\r\n");
return ERROR_TIMEOUT;
}
} else {
break;
}
}
SET_REG(NAND + NAND_CMD, 0);
wait_for_ready(500);
return 0;
}
/* Wait for the codec to be ready, write the verb, then wait for the
* codec to be have a valid response.
*/
static int exec_one_verb(uint32_t base, uint32_t val, uint32_t *response)
{
if (wait_for_ready(base) == -1)
return -1;
writel(val, base + HDA_ICII_COMMAND_REG);
if (wait_for_response(base, response) == -1)
return -1;
return 0;
}
int rd_data( void )
{
int d;
wait_for_ready();
gpio_hdc( 1 );
gpio_hcs_l( 0 );
gpio_hrd_l( 0 );
d = rd_gpio_hdb( );
gpio_hrd_l( 1 );
gpio_hcs_l( 1 );
return d;
}
DRESULT dataflash_ioctl(BYTE ctrl, void *buff) {
DRESULT res;
BYTE *ptr = buff;
res = RES_ERROR;
if (ctrl == CTRL_POWER) {
switch (*ptr) {
case 0: /* Sub control code == 0 (POWER_OFF) */
dataflash_powerdown();
res = RES_OK;
break;
case 1: /* Sub control code == 1 (POWER_ON) */
dataflash_resume();
res = RES_OK;
break;
case 2: /* Sub control code == 2 (POWER_GET) */
// TODO: figure out a way to retrieve the powerstate
*(ptr+1) = (BYTE)1;
res = RES_OK;
break;
default :
res = RES_PARERR;
}
} else {
if (status & STA_NOINIT) return RES_NOTRDY;
switch (ctrl) {
case CTRL_SYNC:
wait_for_ready();
res = RES_OK;
break;
case GET_SECTOR_COUNT:
// TODO: read from device ID register
*(WORD*)buff = MAX_PAGE/2;
res = RES_OK;
break;
case GET_SECTOR_SIZE:
*(WORD*)buff = 512;
res = RES_OK;
break;
case GET_BLOCK_SIZE:
*(WORD*)buff = 1;
res = RES_OK;
break;
default:
res = RES_PARERR;
}
}
return res;
}
static rt_err_t nand_hy27uf_readpage(struct rt_mtd_nand_device *device,
rt_off_t page,
rt_uint8_t *data,
rt_uint32_t data_len,
rt_uint8_t *spare,
rt_uint32_t spare_len)
{
rt_uint32_t i;
rt_err_t result = RT_MTD_EOK;
rt_uint8_t oob_buffer[PAGE_OOB_SIZE];
page = page + device->block_start * device->pages_per_block;
if (page / device->pages_per_block > device->block_end)
{
return -RT_MTD_EIO;
}
if (data != RT_NULL && data_len != 0)
{
NAND_COMMAND = NAND_CMD_READ0;
NAND_ADDRESS = 0 & 0xFF;
NAND_ADDRESS = 0 >> 8;
NAND_ADDRESS = page & 0xFF;
NAND_ADDRESS = page >> 8;
NAND_COMMAND = NAND_CMD_READ3;
wait_for_ready();
for (i = 0; i < PAGE_DATA_SIZE; i ++)
data[i] = NAND_DATA;
for (i = 0; i < PAGE_OOB_SIZE; i ++)
oob_buffer[i] = NAND_DATA;
/* verify ECC */
#ifdef RT_USING_NFTL
if (nftl_ecc_verify256(data, PAGE_DATA_SIZE, oob_buffer) != RT_MTD_EOK)
{
rt_kprintf("ECC error, block: %d, page: %d!\n", page / device->pages_per_block,
page % device->pages_per_block);
result = RT_MTD_EECC;
}
#endif
if (spare != RT_NULL && spare_len > 0)
{
memcpy(spare, oob_buffer, spare_len);
}
}
status_t
periph_get_media_status(scsi_periph_handle_info *handle)
{
scsi_periph_device_info *device = handle->device;
scsi_ccb *request;
err_res res;
status_t err;
ACQUIRE_BEN(&device->mutex);
// removal requests are returned to exactly one handle
// (no real problem, as noone check medias status "by mistake")
if (device->removal_requested) {
device->removal_requested = false;
err = B_DEV_MEDIA_CHANGE_REQUESTED;
goto err;
}
// if there is a pending error (read: media has changed), return once per handle
err = handle->pending_error;
if (err != B_OK) {
handle->pending_error = B_OK;
goto err;
}
SHOW_FLOW0( 3, "" );
RELEASE_BEN(&device->mutex);
// finally, ask the device itself
request = device->scsi->alloc_ccb(device->scsi_device);
if (request == NULL)
return B_NO_MEMORY;
res = wait_for_ready(device, request);
device->scsi->free_ccb(request);
SHOW_FLOW(3, "error_code: %x", (int)res.error_code);
return res.error_code;
err:
RELEASE_BEN(&device->mutex);
return err;
}
int nand_bank_reset(int bank, int timeout) {
SET_REG(NAND + NAND_CONFIG,
((NANDSetting1 & NAND_CONFIG_SETTING1MASK) << NAND_CONFIG_SETTING1SHIFT) | ((NANDSetting2 & NAND_CONFIG_SETTING2MASK) << NAND_CONFIG_SETTING2SHIFT)
| (1 << (banksTable[bank] + 1)) | NAND_CONFIG_DEFAULTS);
SET_REG(NAND + NAND_CMD, NAND_CMD_RESET);
int ret = wait_for_ready(timeout);
if(ret == 0) {
ret = nand_bank_reset_helper(bank, timeout);
udelay(1000);
return ret;
} else {
udelay(1000);
return ret;
}
}
int nand_bank_reset(int bank, int timeout) {
SET_REG(NAND + FMCTRL0,
((WEHighHoldTime & FMCTRL_TWH_MASK) << FMCTRL_TWH_SHIFT) | ((WPPulseTime & FMCTRL_TWP_MASK) << FMCTRL_TWP_SHIFT)
| (1 << (banksTable[bank] + 1)) | FMCTRL0_ON | FMCTRL0_WPB);
SET_REG(NAND + NAND_CMD, NAND_CMD_RESET);
int ret = wait_for_ready(timeout);
if(ret == 0) {
ret = wait_for_command_done(bank, timeout);
udelay(1000);
return ret;
} else {
udelay(1000);
return ret;
}
}
static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
{
int i;
for (i = 3; i >= 0; i--) {
if (codec_mask & (1 << i))
codec_init(dev, base, i);
}
for (i = 0; i < pc_beep_verbs_size; i++) {
if (wait_for_ready(base) == -1)
return;
write32(base + 0x60, pc_beep_verbs[i]);
if (wait_for_valid(base) == -1)
return;
}
}
void processDataBlock(int len,int id)
{
//Navigation data packet. See manual page 7 paragraph 3.2
if ((len==55)&&(id==0x70))
{
wait_for_ready(54);
//Status data.
//Not used for now.
for (uint8_t i=0;i!=4;i++)
info[i]=hal.uartB->read();
//Read 9x floats from buffer.
for (uint8_t i=0;i!=9;i++)
{
for (uint8_t j=0;j!=4;j++)
fl[j]=hal.uartB->read();
nav_data[i] = *(float *)&fl;
}
//Read GPS data (not used?)
for (uint8_t j=0;j!=4;j++)
fl[j]=hal.uartB->read();
latitude = (fl[0] << 24) | (fl[1] << 16) | (fl[2] << 8) | fl[3];
for (uint8_t j=0;j!=4;j++)
fl[j]=hal.uartB->read();
longitude = (fl[0] << 24) | (fl[1] << 16) | (fl[2] << 8) | fl[3];
// Last is GPS height
for (uint8_t j=0;j!=4;j++)
fl[j]=hal.uartB->read();
nav_data[9] = *(float *)&fl;
//Dump ok there. Ready for output.
data_ready=1;
}
else
{
}
}
static void codec_init(u32 base, int addr)
{
u32 dword;
/* 1 */
if (wait_for_ready(base) == -1)
return;
dword = (addr << 28) | 0x000f0000;
write32(base + 0x60, dword);
if (wait_for_valid(base) == -1)
return;
dword = read32(base + 0x64);
/* 2 */
printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
}
int cmd_spi_tx(spi_t *spi,const char *data, size_t len, int timeout_ms)
{
if(len > CMD_MAX_SIZE)
return -CMD_ERR_TOO_LONG;
/* wait for ready from slave */
int result = wait_for_ready(spi, timeout_ms, NULL);
if(result < 0) {
return result;
}
/* setup TX command header with data */
buffer[0] = CMD_TX;
buffer[1] = (char)(len & 0xff);
memcpy(buffer+2,data,len);
/* send to slave */
return spi_transmit(spi,NULL,buffer,len+2);
}
int nand_erase(int bank, int block) {
int pageAddr;
if(bank >= Data.banksTotal)
return ERROR_ARG;
if(block >= Data.blocksPerBank)
return ERROR_ARG;
pageAddr = block * Data.pagesPerBlock;
SET_REG(NAND + NAND_CONFIG,
((NANDSetting1 & NAND_CONFIG_SETTING1MASK) << NAND_CONFIG_SETTING1SHIFT) | ((NANDSetting2 & NAND_CONFIG_SETTING2MASK) << NAND_CONFIG_SETTING2SHIFT)
| (1 << (banksTable[bank] + 1)) | NAND_CONFIG_DEFAULTS);
SET_REG(NAND + NAND_CON, 0x7E0);
SET_REG(NAND + NAND_CMD, 0x60);
SET_REG(NAND + NAND_CONFIG4, 2);
SET_REG(NAND + NAND_CONFIG3, pageAddr);
SET_REG(NAND + NAND_CON, NAND_CON_ADDRESSDONE);
if(wait_for_address_complete(500) != 0) {
bufferPrintf("nand (nand_erase): wait for address complete failed\r\n");
goto FIL_erase_error;
}
SET_REG(NAND + NAND_CMD, 0xD0);
wait_for_ready(500);
while((nand_read_status() & (1 << 6)) == 0);
if(nand_read_status() & 0x1)
return -1;
else
return 0;
FIL_erase_error:
return -1;
}
int nand_erase(int bank, int block) {
int pageAddr;
if(bank >= Geometry.banksTotal)
return ERROR_ARG;
if(block >= Geometry.blocksPerBank)
return ERROR_ARG;
pageAddr = block * Geometry.pagesPerBlock;
SET_REG(NAND + FMCTRL0,
((WEHighHoldTime & FMCTRL_TWH_MASK) << FMCTRL_TWH_SHIFT) | ((WPPulseTime & FMCTRL_TWP_MASK) << FMCTRL_TWP_SHIFT)
| (1 << (banksTable[bank] + 1)) | FMCTRL0_ON | FMCTRL0_WPB);
SET_REG(NAND + FMCTRL1, FMCTRL1_CLEARALL);
SET_REG(NAND + NAND_CMD, 0x60);
SET_REG(NAND + FMANUM, 2);
SET_REG(NAND + FMADDR0, pageAddr);
SET_REG(NAND + FMCTRL1, FMCTRL1_DOTRANSADDR);
if(wait_for_address_done(500) != 0) {
bufferPrintf("nand (nand_erase): wait for address complete failed\r\n");
goto FIL_erase_error;
}
SET_REG(NAND + NAND_CMD, 0xD0);
wait_for_ready(500);
while((nand_read_status() & (1 << 6)) == 0);
if(nand_read_status() & 0x1)
return -1;
else
return 0;
FIL_erase_error:
return -1;
}
static rt_err_t nand_hy27uf_readpage(struct rt_mtd_nand_device *device,
rt_off_t page,
rt_uint8_t *data,
rt_uint32_t data_len,
rt_uint8_t *spare,
rt_uint32_t spare_len)
{
rt_uint32_t i;
rt_err_t result = RT_MTD_EOK;
rt_uint8_t oob_buffer[PAGE_OOB_SIZE];
page = page + device->block_start * device->pages_per_block;
if (page/device->pages_per_block > device->block_end)
{
return -RT_MTD_EIO;
}
if (data != RT_NULL && data_len != 0)
{
NAND_COMMAND = NAND_CMD_READ0;
NAND_ADDRESS = 0 & 0xFF;
NAND_ADDRESS = 0 >> 8;
NAND_ADDRESS = page & 0xFF;
NAND_ADDRESS = page >> 8;
NAND_COMMAND = NAND_CMD_READ3;
wait_for_ready();
for (i = 0; i < PAGE_DATA_SIZE; i ++)
data[i] = NAND_DATA;
for (i = 0; i < PAGE_OOB_SIZE; i ++)
oob_buffer[i] = NAND_DATA;
if (spare != RT_NULL && spare_len > 0)
{
memcpy(spare, oob_buffer, spare_len);
}
}
