/* Called when a transfer is finished and data is ready/written */
static void mc13783_xfer_complete_cb(struct spi_transfer_desc *xfer)
{
if (xfer->count != 0)
return;
wakeup_signal(&mc13783_spi_wake);
}
/* GPIO interrupt handler for mc13783 */
void mc13783_event(void)
{
/* Mask the interrupt (unmasked when PMIC thread services it). */
imx31_regclr32(&MC13783_GPIO_IMR, 1ul << MC13783_GPIO_LINE);
MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
wakeup_signal(&mc13783_svc_wake);
}
void mc13783_close(void)
{
unsigned int thread_id = mc13783_thread_id;
if (thread_id == 0)
return;
mc13783_thread_id = 0;
wakeup_signal(&mc13783_svc_wake);
thread_wait(thread_id);
spi_disable_module(&mc13783_spi);
}
FOR_EACH_OUT_EP_AND_EP0(i, ep)
{
endpoints[ep][DIR_OUT].active = false;
endpoints[ep][DIR_OUT].busy = false;
endpoints[ep][DIR_OUT].status = -1;
if(endpoints[ep][DIR_OUT].wait)
wakeup_signal(&endpoints[ep][DIR_OUT].complete);
endpoints[ep][DIR_OUT].wait = false;
if(DOEPCTL(ep) & DEPCTL_epena)
DOEPCTL(ep) = DEPCTL_snak;
else
DOEPCTL(ep) = 0;
}
static void reset_endpoints(void)
{
unsigned i;
int ep;
/* disable all endpoints except EP0 */
FOR_EACH_IN_EP_AND_EP0(i, ep)
{
endpoints[ep][DIR_IN].active = false;
endpoints[ep][DIR_IN].busy = false;
endpoints[ep][DIR_IN].status = -1;
if(endpoints[ep][DIR_IN].wait)
wakeup_signal(&endpoints[ep][DIR_IN].complete);
endpoints[ep][DIR_IN].wait = false;
if(DIEPCTL(ep) & DEPCTL_epena)
DIEPCTL(ep) = DEPCTL_snak;
else
DIEPCTL(ep) = 0;
}
