void comx_fd_device::comx_io_w(offs_t offset, UINT8 data)
{
if (offset == 2)
{
if (m_q)
{
/*
bit description
0 A0
1 A1
2 DRIVE0
3 DRIVE1
4 F9 DISB
5 SIDE SELECT
*/
// latch data to F3
m_addr = data & 0x03;
if (BIT(data, 2))
{
wd17xx_set_drive(m_fdc, 0);
}
else if (BIT(data, 3))
{
wd17xx_set_drive(m_fdc, 1);
}
m_disb = !BIT(data, 4);
update_ef4();
wd17xx_set_side(m_fdc, BIT(data, 5));
}
else
{
// write data to WD1770
wd17xx_w(m_fdc, m_addr, data);
}
}
}
void abc1600_state::write_io(offs_t offset, UINT8 data)
{
address_space *program = m_maincpu->memory().space(AS_PROGRAM);
if (X12)
{
if (X11)
{
switch (A10_A9_A8)
{
case IOWR0:
iowr0_w(*program, offset, data);
break;
case IOWR1:
iowr1_w(*program, offset, data);
break;
case IOWR2:
iowr2_w(*program, offset, data);
break;
case FW:
if (!A7)
{
if (A0)
fw1_w(*program, offset, data);
else
fw0_w(*program, offset, data);
}
else
{
logerror("Unmapped write to virtual I/O %06x : %02x\n", offset, data);
}
break;
case DMAMAP:
dmamap_w(*program, offset, data);
break;
case SPEC_CONTR_REG:
spec_contr_reg_w(*program, offset, data);
break;
default:
logerror("Unmapped write to virtual I/O %06x : %02x\n", offset, data);
}
}
else
{
switch (A10_A9_A8)
{
case FLP:
wd17xx_w(m_fdc, A2_A1, data);
break;
case CRT:
if (A0)
mc6845_register_w(m_crtc, 0, data);
else
mc6845_address_w(m_crtc, 0, data);
break;
case DRT:
z80dart_ba_cd_w(m_dart, A2_A1 ^ 0x03, data);
break;
case DMA0:
m_dma0->write(data);
break;
case DMA1:
m_dma1->write(data);
break;
case DMA2:
m_dma2->write(data);
break;
case SCC:
scc8530_w(m_scc, A1_A2, data);
break;
case CIO:
m_cio->write(*program, A2_A1, data);
break;
}
}
}
}
