void ls2085a_handle_phy_interface_sgmii(int dpmac_id) { int lane, slot; struct mii_dev *bus; struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; switch (serdes1_prtcl) { } switch (serdes2_prtcl) { case 0x07: case 0x08: case 0x49: lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 + (dpmac_id - 9)); slot = lane_to_slot_fsm2[lane]; switch (++slot) { case 1: break; case 3: break; case 4: /* Slot housing a SGMII riser card? */ wriop_set_phy_address(dpmac_id, riser_phy_addr[dpmac_id - 9]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT4; bus = mii_dev_for_muxval(EMI1_SLOT4); wriop_set_mdio(dpmac_id, bus); dpmac_info[dpmac_id].phydev = phy_connect( dpmac_info[dpmac_id].bus, dpmac_info[dpmac_id].phy_addr, NULL, dpmac_info[dpmac_id].enet_if); phy_config(dpmac_info[dpmac_id].phydev); break; case 5: break; case 6: /* Slot housing a SGMII riser card? */ wriop_set_phy_address(dpmac_id, riser_phy_addr[dpmac_id - 13]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT6; bus = mii_dev_for_muxval(EMI1_SLOT6); wriop_set_mdio(dpmac_id, bus); break; } break; default: printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", serdes2_prtcl); break; } }
void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) { int lane = 0, slot; struct mii_dev *bus; struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; switch (serdes1_prtcl) { case 0x33: switch (dpmac_id) { case 1: case 2: case 3: case 4: lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A); break; case 5: case 6: case 7: case 8: lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B); break; case 9: case 10: case 11: case 12: lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C); break; case 13: case 14: case 15: case 16: lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D); break; } slot = lane_to_slot_fsm1[lane]; switch (++slot) { case 1: /* Slot housing a QSGMII riser card? */ wriop_set_phy_address(dpmac_id, dpmac_id - 1); dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); wriop_set_mdio(dpmac_id, bus); dpmac_info[dpmac_id].phydev = phy_connect( dpmac_info[dpmac_id].bus, dpmac_info[dpmac_id].phy_addr, NULL, dpmac_info[dpmac_id].enet_if); phy_config(dpmac_info[dpmac_id].phydev); break; case 3: break; case 4: break; case 5: break; case 6: break; } break; default: printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", serdes1_prtcl); break; } qsgmii_configure_repeater(dpmac_id); }
void ls2080a_handle_phy_interface_sgmii(int dpmac_id) { int lane, slot; struct mii_dev *bus; struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; int *riser_phy_addr; char *env_hwconfig = getenv("hwconfig"); if (hwconfig_f("xqsgmii", env_hwconfig)) riser_phy_addr = &xqsgii_riser_phy_addr[0]; else riser_phy_addr = &sgmii_riser_phy_addr[0]; if (dpmac_id > WRIOP1_DPMAC9) goto serdes2; switch (serdes1_prtcl) { case 0x07: lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id); slot = lane_to_slot_fsm1[lane]; switch (++slot) { case 1: /* Slot housing a SGMII riser card? */ wriop_set_phy_address(dpmac_id, riser_phy_addr[dpmac_id - 1]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); wriop_set_mdio(dpmac_id, bus); dpmac_info[dpmac_id].phydev = phy_connect( dpmac_info[dpmac_id].bus, dpmac_info[dpmac_id].phy_addr, NULL, dpmac_info[dpmac_id].enet_if); phy_config(dpmac_info[dpmac_id].phydev); break; case 2: /* Slot housing a SGMII riser card? */ wriop_set_phy_address(dpmac_id, riser_phy_addr[dpmac_id - 1]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT2; bus = mii_dev_for_muxval(EMI1_SLOT2); wriop_set_mdio(dpmac_id, bus); dpmac_info[dpmac_id].phydev = phy_connect( dpmac_info[dpmac_id].bus, dpmac_info[dpmac_id].phy_addr, NULL, dpmac_info[dpmac_id].enet_if); phy_config(dpmac_info[dpmac_id].phydev); break; case 3: break; case 4: break; case 5: break; case 6: break; } break; default: printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", __func__ , serdes1_prtcl); break; } serdes2: switch (serdes2_prtcl) { case 0x07: case 0x08: case 0x49: lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 + (dpmac_id - 9)); slot = lane_to_slot_fsm2[lane]; switch (++slot) { case 1: break; case 3: break; case 4: /* Slot housing a SGMII riser card? */ wriop_set_phy_address(dpmac_id, riser_phy_addr[dpmac_id - 9]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT4; bus = mii_dev_for_muxval(EMI1_SLOT4); wriop_set_mdio(dpmac_id, bus); dpmac_info[dpmac_id].phydev = phy_connect( dpmac_info[dpmac_id].bus, dpmac_info[dpmac_id].phy_addr, NULL, dpmac_info[dpmac_id].enet_if); phy_config(dpmac_info[dpmac_id].phydev); break; case 5: break; case 6: /* Slot housing a SGMII riser card? */ wriop_set_phy_address(dpmac_id, riser_phy_addr[dpmac_id - 13]); dpmac_info[dpmac_id].board_mux = EMI1_SLOT6; bus = mii_dev_for_muxval(EMI1_SLOT6); wriop_set_mdio(dpmac_id, bus); break; } break; default: printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", __func__, serdes2_prtcl); break; } }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) int i, interface; struct memac_mdio_info mdio_info; struct mii_dev *dev; struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 srds_s1; struct memac_mdio_controller *reg; srds_s1 = in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; /* Register the EMI 1 */ fm_memac_mdio_init(bis, &mdio_info); reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; /* Register the EMI 2 */ fm_memac_mdio_init(bis, &mdio_info); switch (srds_s1) { case 0x2A: wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1); wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2); wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); break; default: printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n", srds_s1); break; } for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) { interface = wriop_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); wriop_set_mdio(i, dev); break; default: break; } } for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) { switch (wriop_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); wriop_set_mdio(i, dev); break; default: break; } } /* Load CORTINA CS4340 PHY firmware */ load_phy_firmware(); cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ #ifdef CONFIG_PHY_AQUANTIA /* * Export functions to be used by AQ firmware * upload application */ gd->jt->strcpy = strcpy; gd->jt->mdelay = mdelay; gd->jt->mdio_get_current_dev = mdio_get_current_dev; gd->jt->phy_find_by_mask = phy_find_by_mask; gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) int i, interface; struct memac_mdio_info mdio_info; struct mii_dev *dev; struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct memac_mdio_controller *reg; u32 srds_s1, cfg; cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & FSL_CHASSIS3_SRDS1_PRTCL_MASK; cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; /* Register the EMI 1 */ fm_memac_mdio_init(bis, &mdio_info); reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; /* Register the EMI 2 */ fm_memac_mdio_init(bis, &mdio_info); switch (srds_s1) { case 0x1D: /* * XFI does not need a PHY to work, but to avoid U-boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC error. */ wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a); wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1); wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR); wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR); wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR); wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR); wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR); wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR); wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR); wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR); break; default: printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n", srds_s1); break; } for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) { interface = wriop_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_QSGMII: dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); wriop_set_mdio(i, dev); break; default: break; } } dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); wriop_set_mdio(WRIOP1_DPMAC2, dev); cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }