/**
* init
*
* Initialize CC1101
*/
void CC1101::init(void)
{
spi.init(); // Initialize SPI interface
pinMode(GDO0, INPUT); // Config GDO0 as input
reset(); // Reset CC1101
// Configure PATABLE
writeBurstReg(CC1101_PATABLE, (byte*)paTable, 8);
}
/**
* sendData
*
* Send data packet via RF
*
* 'packet' Packet to be transmitted
*
* Return:
* True if the transmission succeeds
* False otherwise
*/
boolean CC1101::sendData(CCPACKET packet)
{
// Enter RX state
setRxState();
// Check that the RX state has been entered
while (readStatusReg(CC1101_MARCSTATE) != 0x0D)
delay(1);
delayMicroseconds(500);
// Set data length at the first position of the TX FIFO
writeReg(CC1101_TXFIFO, packet.length);
// Write data into the TX FIFO
writeBurstReg(CC1101_TXFIFO, packet.data, packet.length);
// CCA enabled: will enter TX state only if the channel is clear
cmdStrobe(CC1101_STX);
// Check that TX state is being entered (state = RXTX_SETTLING)
if(readStatusReg(CC1101_MARCSTATE) != 0x15)
return false;
// Wait for the sync word to be transmitted
wait_GDO0_high();
// Wait until the end of the packet transmission
wait_GDO0_low();
// Flush TX FIFO. Don't uncomment
// cmdStrobe(CC1101_SFTX);
// Enter back into RX state
setRxState();
// Check that the TX FIFO is empty
if((readStatusReg(CC1101_TXBYTES) & 0x7F) == 0)
return true;
return false;
}
/**
* sendData
*
* Send data packet via RF
*
* 'packet' Packet to be transmitted. First byte is the destination address
*
* Return:
* True if the transmission succeeds
* False otherwise
*/
boolean CC1101::sendData(CCPACKET packet)
{
byte marcState;
bool res = false;
// Declare to be in Tx state. This will avoid receiving packets whilst
// transmitting
rfState = RFSTATE_TX;
// Enter RX state
setRxState();
// Check that the RX state has been entered
while (((marcState = readStatusReg(CC1101_MARCSTATE)) & 0x1F) != 0x0D)
{
if (marcState == 0x11) // RX_OVERFLOW
flushRxFifo(); // flush receive queue
}
delayMicroseconds(500);
// Set data length at the first position of the TX FIFO
writeReg(CC1101_TXFIFO, packet.length);
// Write data into the TX FIFO
writeBurstReg(CC1101_TXFIFO, packet.data, packet.length);
// CCA enabled: will enter TX state only if the channel is clear
setTxState();
// Check that TX state is being entered (state = RXTX_SETTLING)
marcState = readStatusReg(CC1101_MARCSTATE) & 0x1F;
if((marcState != 0x13) && (marcState != 0x14) && (marcState != 0x15))
{
setIdleState(); // Enter IDLE state
flushTxFifo(); // Flush Tx FIFO
setRxState(); // Back to RX state
// Declare to be in Rx state
rfState = RFSTATE_RX;
return false;
}
// Wait for the sync word to be transmitted
wait_GDO0_high();
// Wait until the end of the packet transmission
wait_GDO0_low();
// Check that the TX FIFO is empty
if((readStatusReg(CC1101_TXBYTES) & 0x7F) == 0)
res = true;
setIdleState(); // Enter IDLE state
flushTxFifo(); // Flush Tx FIFO
// Enter back into RX state
setRxState();
// Declare to be in Rx state
rfState = RFSTATE_RX;
return res;
}
