static void define_font(uint32 id, uint32 width, uint32 height, uint8 *bits)
{
dprintf("define_font(%u, %u,%u, %p)\n", id, width, height, bits);
writeFIFO(SVGA_CMD_DEFINE_BITMAP);
writeFIFO(id);
writeFIFO(width);
writeFIFO(height);
while (height--) writeFIFO(bit_reversed[*bits++]);
}
static void copy_bitmap(uint32 id, uint32 src_x, uint32 src_y, uint32 dst_x, uint32 dst_y, uint32 width, uint32 height, uint32 fg, uint32 bg)
{
writeFIFO(SVGA_CMD_RECT_BITMAP_COPY);
writeFIFO(id);
writeFIFO(src_x);
writeFIFO(src_y);
writeFIFO(dst_x);
writeFIFO(dst_y);
writeFIFO(width);
writeFIFO(height);
writeFIFO(fg);
writeFIFO(bg);
}
static void copy_rect(uint32 src_x, uint32 src_y, uint32 dst_x, uint32 dst_y, uint32 width, uint32 height)
{
writeFIFO(SVGA_CMD_RECT_COPY);
writeFIFO(src_x);
writeFIFO(src_y);
writeFIFO(dst_x);
writeFIFO(dst_y);
writeFIFO(width);
writeFIFO(height);
}
static void invert_rect(uint32 x, uint32 y, uint32 width, uint32 height)
{
#define GXinvert 0xa
writeFIFO(SVGA_CMD_RECT_ROP_FILL);
writeFIFO(0); // color
writeFIFO(x);
writeFIFO(y);
writeFIFO(width);
writeFIFO(height);
writeFIFO(GXinvert);
}
static void fill_rect(uint32 color, uint32 x, uint32 y, uint32 width, uint32 height)
{
writeFIFO(SVGA_CMD_RECT_FILL);
writeFIFO(color);
writeFIFO(x);
writeFIFO(y);
writeFIFO(width);
writeFIFO(height);
//dprintf("fill_rect(%6x,%u,%u,%u,%u)\n", color, x, y, width, height);
}
int main()
{
// while(1)
// {
// writeFIFO(1);
// usleep(1000*1000*1);
// }
int i = 0;
while(1)
{
writeFIFO(i%2);
i++;
usleep(1000*1000*1);
}
return 0;
// exit(EXIT_SUCCESS);
}
inline
ssize_t writeFIFO(const int nPipe, const std::string& message)
{
return writeFIFO(nPipe, message.c_str(), message.size());
}
void __ISR(_I2C_2_VECTOR, ipl3) _SlaveI2CHandler(void) {
int temp;
// check for MASTER and Bus events and respond accordingly
if (IFS1bits.I2C2MIF == 1) {
IFS1CLR = 0x02000000;
return;
}
if (IFS1bits.I2C2BIF == 1) {
IFS1CLR = 0x02000000;
return;
}
// handle the incoming message
if ((I2C2STATbits.R_W == 0) && (I2C2STATbits.D_A == 0)) {
// R/W bit = 0 --> indicates data transfer is input to slave
// D/A bit = 0 --> indicates last byte was address
temp = I2C2RCV;
I2C2CONbits.SCLREL = 1; // release the clock
} else if ((I2C2STATbits.R_W == 0) && (I2C2STATbits.D_A == 1)) {
// R/W bit = 0 --> indicates data transfer is input to slave
// D/A bit = 1 --> indicates last byte was data
// mLED_3_On();
// mLED_2_On();
// writing data to our module, just store it in adcSample
//dataRead = SlaveReadI2C2();
if (writeFIFO(g_i2c_receiveBuffer, I2C2RCV) > 0) {
// release the clock to restart I2C
I2C2CONbits.SCLREL = 1; // release clock stretch bit
g_receiveBufferFull = FALSE;
} else {
temp = I2C2RCV;
g_receiveBufferFull = TRUE;
I2C2CONbits.SCLREL = 1;
}
} else if ((I2C2STATbits.R_W == 1) && (I2C2STATbits.D_A == 0)) {
temp = I2C2RCV;
temp = readFIFO(g_i2c_transmitBuffer);
if (temp > 0) {
I2C2TRN = temp & 0xFF;
} else {
I2C2TRN = 0;
}
I2C2CONbits.SCLREL = 1;
} else if ((I2C2STATbits.R_W == 1) && (I2C2STATbits.D_A == 1)) {
// R/W bit = 1 --> indicates data transfer is output from slave
// D/A bit = 1 --> indicates last byte was data
// output the data until the MASTER terminates the
// transfer with a NACK, continuing reads return 0
temp = readFIFO(g_i2c_transmitBuffer);
if (temp > 0) {
I2C2TRN = temp & 0xFF;
} else {
I2C2TRN = 0;
}
I2C2CONbits.SCLREL = 1;
}
// finally clear the slave interrupt flag
IFS1CLR = 0x02000000;
}
void _processSidNetCommand(void) {
UINT8 responseBuffer[100];
int responseLength = 0,i;
switch (SIDNetCmd.cmd) {
case FLUSH:
sidPlayerFlush(SIDNetCmd.sidPlayer);
responseBuffer[responseLength++] = OK;
break;
case TRY_SET_SID_COUNT:
responseBuffer[responseLength++] = OK;
break;
case MUTE:
responseBuffer[responseLength++] = OK;
break;
case TRY_RESET:
//resetFifo(playFifo);
//playing = false;
responseBuffer[responseLength++] = OK;
break;
case GET_VERSION: {
responseBuffer[responseLength++] = VERSION;
responseBuffer[responseLength++] = SID_NETWORK_PROTOCOL_VERSION;
break;
}
case TRY_SET_SAMPLING:
responseBuffer[responseLength++] = OK;
break;
case TRY_SET_CLOCKING:
responseBuffer[responseLength++] = OK;
break;
case GET_CONFIG_COUNT:
responseBuffer[responseLength++] = COUNT;
responseBuffer[responseLength++] = 1;
break;
case GET_CONFIG_INFO: {
responseBuffer[responseLength++] = INFO;
responseBuffer[responseLength++] = 0;
strcpy(&responseBuffer[0] + responseLength,SID_PI);
responseLength += sizeof SID_PI;
responseBuffer[responseLength++] = 0;
break;
}
case SET_SID_POSITION:
responseBuffer[responseLength++] = OK;
break;
case TRY_SET_SID_MODEL:
responseBuffer[responseLength++] = OK;
break;
case TRY_WRITE: {
if((FIFOCount(getSIDPlayerBuffer(SIDNetCmd.sidPlayer))
+ SIDNetCmd.dataLength) >
FIFOSize(getSIDPlayerBuffer(SIDNetCmd.sidPlayer))) {
#ifdef DEBUG
char buf[100];
sprintf(buf,"Player buffer full\r\n\0");
writeStringUART(buf,strlen(buf));
#endif
responseBuffer[responseLength++] = BUSY;
break;
}
for(i=0;i<SIDNetCmd.dataLength;i++) {
if(writeFIFO(getSIDPlayerBuffer(SIDNetCmd.sidPlayer),SIDNetCmd.data[i]) < 0) {
responseBuffer[responseLength++] = ERR;
#ifdef DEBUG
char buf[100];
sprintf(buf,"Cannot write to player buffer\r\n\0");
writeStringUART(buf,strlen(buf));
#endif
break;
}
}
responseBuffer[responseLength++] = OK;
break;
}
default:
responseBuffer[responseLength++] = OK;
break;
}
for(i=0;i<responseLength;i++) {
writeFIFO(SIDNetCmd.respFifo,responseBuffer[i]);
}
}
