Пример #1
0
static void plat_restore_el3_dormant_data()
{
	struct _el3_dormant_data *p = &el3_dormant_data[0];

	if (p->mp0_l2actlr_el1 == 0 && p->mp0_l2ectlr_el1==0)
		panic();
	write_l2actlr(p->mp0_l2actlr_el1);
	write_l2ectlr(p->mp0_l2ectlr_el1);

	//restore L2RSTDIRSABLE
	mmio_write_32(MP0_CA7L_CACHE_CONFIG,
		      (mmio_read_32(MP0_CA7L_CACHE_CONFIG) & ~L2RSTDISABLE)
		      | (p->mp0_l2rstdisable & L2RSTDISABLE));
}
Пример #2
0
int workaround_826319(unsigned long mpidr)
{
        unsigned long l2actlr;

        /** only apply on 1st CPU of each cluster **/
        if (mpidr & MPIDR_CPU_MASK)
                return 0;

        /** CONFIG_ARM_ERRATA_826319=y (for 6595/6752)
         * Prog CatB Rare,
         * System might deadlock if a write cannot complete until read data is accepted	
         * worksround: (L2ACTLR[14]=0, L2ACTLR[3]=1).
         * L2ACTLR must be written before MMU on and any ACE, CHI or ACP traffic.
         **/
        l2actlr = read_l2actlr();
        l2actlr = (l2actlr & ~(1<<14)) | (1<<3);
        write_l2actlr(l2actlr);

        return 0;
}
Пример #3
0
/*******************************************************************************
 * MTK_platform handler called when an affinity instance has just been powered on after
 * having been suspended earlier. The level and mpidr determine the affinity
 * instance.
 * TODO: At the moment we reuse the on finisher and reinitialize the secure
 * context. Need to implement a separate suspend finisher.
 ******************************************************************************/
int mt_affinst_suspend_finish(unsigned long mpidr,
			       unsigned int afflvl,
			       unsigned int state)
{
	int rc = PSCI_E_SUCCESS;

	switch (afflvl) {
	case MPIDR_AFFLVL2:
                if (state == PSCI_STATE_OFF) {
                        struct _el3_dormant_data *p = &el3_dormant_data[0];

                        if (p->mp0_l2actlr_el1 == 0 && p->mp0_l2ectlr_el1==0)
                                panic();
                        write_l2actlr(p->mp0_l2actlr_el1);
                        write_l2ectlr(p->mp0_l2ectlr_el1);

                        //restore L2RSTDIRSABLE
                        mmio_write_32(MP0_CA7L_CACHE_CONFIG, 
                                      (mmio_read_32(MP0_CA7L_CACHE_CONFIG) & ~L2RSTDISABLE) 
                                      | (p->mp0_l2rstdisable & L2RSTDISABLE));

                        gic_setup();
                        gic_dist_restore();
                }

                break;

	case MPIDR_AFFLVL1:
	case MPIDR_AFFLVL0:
                return mt_affinst_on_finish(mpidr, afflvl, state);

	default:
		assert(0);
	}

	return rc;
}