int lpc_early_init(const void *blob, int node, pci_dev_t dev)
{
struct reg_info {
u32 base;
u32 size;
} values[4], *ptr;
int count;
int i;
count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
(u32 *)values, sizeof(values) / sizeof(u32));
if (count < 0)
return -EINVAL;
/* Set COM1/COM2 decode range */
x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
GAMEL_LPC_EN | COMA_LPC_EN);
/* Write all registers but use 0 if we run out of data */
count = count * sizeof(u32) / sizeof(values[0]);
for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
u32 reg = 0;
if (i < count)
reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
}
return 0;
}
/*
* TODO:
*
* This whole routine should be removed until we fully convert the ICH SPI
* driver to DM and make use of DT to pass the bios control register offset
*/
static void unprotect_spi_flash(void)
{
u32 bc;
bc = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
bc |= 0x1; /* unprotect the flash */
x86_pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
}
static void unprotect_spi_flash(void)
{
u32 bc;
bc = x86_pci_read_config32(TNC_LPC, 0xd8);
bc |= 0x1; /* unprotect the flash */
x86_pci_write_config32(TNC_LPC, 0xd8, bc);
}
static void qemu_chipset_init(void)
{
u16 device, xbcs;
int pam, i;
/*
* i440FX and Q35 chipset have different PAM register offset, but with
* the same bitfield layout. Here we determine the offset based on its
* PCI device ID.
*/
device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
pam = i440fx ? I440FX_PAM : Q35_PAM;
/*
* Initialize Programmable Attribute Map (PAM) Registers
*
* Configure legacy segments C/D/E/F to system RAM
*/
for (i = 0; i < PAM_NUM; i++)
x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
if (i440fx) {
/*
* Enable legacy IDE I/O ports decode
*
* Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
* However Linux ata_piix driver does sanity check on these two
* registers to see whether legacy ports decode is turned on.
* This is to make Linux ata_piix driver happy.
*/
x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
/* Enable I/O APIC */
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
xbcs |= APIC_EN;
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
enable_pm_piix();
} else {
/* Configure PCIe ECAM base address */
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
CONFIG_PCIE_ECAM_BASE | BAR_EN);
enable_pm_ich9();
}
qemu_fwcfg_init();
}
static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
{
u8 route[16];
u32 reg;
int gpi;
if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
sizeof(route)))
return -EINVAL;
for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
reg |= route[gpi] << (gpi * 2);
x86_pci_write_config32(dev, 0xb8, reg);
return 0;
}
static void enable_pm_piix(void)
{
u8 en;
u16 cmd;
/* Set the PM I/O base */
x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
/* Enable access to the PM I/O space */
cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND);
cmd |= PCI_COMMAND_IO;
x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
/* PM I/O Space Enable (PMIOSE) */
en = x86_pci_read_config8(PIIX_PM, PMREGMISC);
en |= PMIOSE;
x86_pci_write_config8(PIIX_PM, PMREGMISC, en);
}
static void enable_pm_ich9(void)
{
/* Set the PM I/O base */
x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
}
int board_pci_post_scan(struct pci_controller *hose)
{
int ret = 0;
u16 device, xbcs;
int pam, i;
pci_dev_t vga;
ulong start;
/*
* i440FX and Q35 chipset have different PAM register offset, but with
* the same bitfield layout. Here we determine the offset based on its
* PCI device ID.
*/
device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
pam = i440fx ? I440FX_PAM : Q35_PAM;
/*
* Initialize Programmable Attribute Map (PAM) Registers
*
* Configure legacy segments C/D/E/F to system RAM
*/
for (i = 0; i < PAM_NUM; i++)
x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
if (i440fx) {
/*
* Enable legacy IDE I/O ports decode
*
* Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
* However Linux ata_piix driver does sanity check on these two
* registers to see whether legacy ports decode is turned on.
* This is to make Linux ata_piix driver happy.
*/
x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
/* Enable I/O APIC */
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
xbcs |= APIC_EN;
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
} else {
/* Configure PCIe ECAM base address */
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
CONFIG_PCIE_ECAM_BASE | BAR_EN);
}
/*
* QEMU emulated graphic card shows in the PCI configuration space with
* PCI vendor id and device id as an artificial pair 0x1234:0x1111.
* It is on PCI bus 0, function 0, but device number is not consistent
* for the two x86 targets it supports. For i440FX and PIIX chipset
* board, it shows as device 2, while for Q35 and ICH9 chipset board,
* it shows as device 1.
*/
vga = i440fx ? I440FX_VGA : Q35_VGA;
start = get_timer(0);
ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE);
debug("BIOS ran in %lums\n", get_timer(start));
return ret;
}
