static int uw2453_write_vco_cfg(struct zd_chip *chip, u16 value)
{
/* vendor driver always sets these upper bits even though the specs say
* they are reserved */
u32 val = 0x40000 | value;
return zd_rfwrite_locked(chip, UW2453_REGWRITE(3, val), RF_RV_BITS);
}
static int uw2453_synth_set_channel(struct zd_chip *chip, int channel,
bool autocal)
{
int r;
int idx = channel - 1;
u32 val;
if (autocal)
val = UW2453_REGWRITE(1, uw2453_autocal_synth[idx]);
else
val = UW2453_REGWRITE(1, uw2453_std_synth[idx]);
r = zd_rfwrite_locked(chip, val, RF_RV_BITS);
if (r)
return r;
return zd_rfwrite_locked(chip,
UW2453_REGWRITE(2, uw2453_synth_divide[idx]), RF_RV_BITS);
}
static int rf2959_set_channel(struct zd_rf *rf, u8 channel)
{
int i, r;
const u32 *rv = rf2959_table[channel-1];
struct zd_chip *chip = zd_rf_to_chip(rf);
for (i = 0; i < 2; i++) {
r = zd_rfwrite_locked(chip, rv[i], RF_RV_BITS);
if (r)
return r;
}
return 0;
}
static int uw2453_set_tx_gain_level(struct zd_chip *chip, int channel)
{
u8 int_value = chip->pwr_int_values[channel - 1];
if (int_value >= ARRAY_SIZE(uw2453_txgain)) {
dev_dbg_f(zd_chip_dev(chip), "can't configure TX gain for "
"int value %x on channel %d\n", int_value, channel);
return 0;
}
return zd_rfwrite_locked(chip,
UW2453_REGWRITE(7, uw2453_txgain[int_value]), RF_RV_BITS);
}
static int uw2453_switch_radio_off(struct zd_rf *rf)
{
int r;
struct zd_chip *chip = zd_rf_to_chip(rf);
static const struct zd_ioreq16 ioreqs[] = {
{ CR11, 0x04 }, { CR251, 0x2f },
};
/* enter IDLE mode */
/* FIXME: shouldn't we go to SLEEP? sent email to zydas */
r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f90), RF_RV_BITS);
if (r)
return r;
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
}
static int uw2453_switch_radio_on(struct zd_rf *rf)
{
int r;
struct zd_chip *chip = zd_rf_to_chip(rf);
struct zd_ioreq16 ioreqs[] = {
{ CR11, 0x00 }, { CR251, 0x3f },
};
/* enter RXTX mode */
r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f94), RF_RV_BITS);
if (r)
return r;
if (zd_chip_is_zd1211b(chip))
ioreqs[1].value = 0x7f;
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
}
static int zd1211_al2230_init_hw(struct zd_rf *rf)
{
int r;
struct zd_chip *chip = zd_rf_to_chip(rf);
static const struct zd_ioreq16 ioreqs_init[] = {
{ ZD_CR15, 0x20 }, { ZD_CR23, 0x40 }, { ZD_CR24, 0x20 },
{ ZD_CR26, 0x11 }, { ZD_CR28, 0x3e }, { ZD_CR29, 0x00 },
{ ZD_CR44, 0x33 }, { ZD_CR106, 0x2a }, { ZD_CR107, 0x1a },
{ ZD_CR109, 0x09 }, { ZD_CR110, 0x27 }, { ZD_CR111, 0x2b },
{ ZD_CR112, 0x2b }, { ZD_CR119, 0x0a }, { ZD_CR10, 0x89 },
/* for newest (3rd cut) AL2300 */
{ ZD_CR17, 0x28 },
{ ZD_CR26, 0x93 }, { ZD_CR34, 0x30 },
/* for newest (3rd cut) AL2300 */
{ ZD_CR35, 0x3e },
{ ZD_CR41, 0x24 }, { ZD_CR44, 0x32 },
/* for newest (3rd cut) AL2300 */
{ ZD_CR46, 0x96 },
{ ZD_CR47, 0x1e }, { ZD_CR79, 0x58 }, { ZD_CR80, 0x30 },
{ ZD_CR81, 0x30 }, { ZD_CR87, 0x0a }, { ZD_CR89, 0x04 },
{ ZD_CR92, 0x0a }, { ZD_CR99, 0x28 }, { ZD_CR100, 0x00 },
{ ZD_CR101, 0x13 }, { ZD_CR102, 0x27 }, { ZD_CR106, 0x24 },
{ ZD_CR107, 0x2a }, { ZD_CR109, 0x09 }, { ZD_CR110, 0x13 },
{ ZD_CR111, 0x1f }, { ZD_CR112, 0x1f }, { ZD_CR113, 0x27 },
{ ZD_CR114, 0x27 },
/* for newest (3rd cut) AL2300 */
{ ZD_CR115, 0x24 },
{ ZD_CR116, 0x24 }, { ZD_CR117, 0xf4 }, { ZD_CR118, 0xfc },
{ ZD_CR119, 0x10 }, { ZD_CR120, 0x4f }, { ZD_CR121, 0x77 },
{ ZD_CR122, 0xe0 }, { ZD_CR137, 0x88 }, { ZD_CR252, 0xff },
{ ZD_CR253, 0xff },
};
static const struct zd_ioreq16 ioreqs_pll[] = {
/* shdnb(PLL_ON)=0 */
{ ZD_CR251, 0x2f },
/* shdnb(PLL_ON)=1 */
{ ZD_CR251, 0x3f },
{ ZD_CR138, 0x28 }, { ZD_CR203, 0x06 },
};
static const u32 rv1[] = {
/* Channel 1 */
0x03f790,
0x033331,
0x00000d,
0x0b3331,
0x03b812,
0x00fff3,
};
static const u32 rv2[] = {
0x000da4,
0x0f4dc5, /* fix freq shift, 0x04edc5 */
0x0805b6,
0x011687,
0x000688,
0x0403b9, /* external control TX power (ZD_CR31) */
0x00dbba,
0x00099b,
0x0bdffc,
0x00000d,
0x00500f,
};
static const u32 rv3[] = {
0x00d00f,
0x004c0f,
0x00540f,
0x00700f,
0x00500f,
};
r = zd_iowrite16a_locked(chip, ioreqs_init, ARRAY_SIZE(ioreqs_init));
if (r)
return r;
if (IS_AL2230S(chip)) {
r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
ARRAY_SIZE(ioreqs_init_al2230s));
if (r)
return r;
}
r = zd_rfwritev_locked(chip, rv1, ARRAY_SIZE(rv1), RF_RV_BITS);
if (r)
return r;
/* improve band edge for AL2230S */
if (IS_AL2230S(chip))
r = zd_rfwrite_locked(chip, 0x000824, RF_RV_BITS);
else
r = zd_rfwrite_locked(chip, 0x0005a4, RF_RV_BITS);
if (r)
return r;
r = zd_rfwritev_locked(chip, rv2, ARRAY_SIZE(rv2), RF_RV_BITS);
if (r)
return r;
r = zd_iowrite16a_locked(chip, ioreqs_pll, ARRAY_SIZE(ioreqs_pll));
if (r)
return r;
r = zd_rfwritev_locked(chip, rv3, ARRAY_SIZE(rv3), RF_RV_BITS);
if (r)
return r;
return 0;
}
static int zd1211b_al2230_init_hw(struct zd_rf *rf)
{
int r;
struct zd_chip *chip = zd_rf_to_chip(rf);
static const struct zd_ioreq16 ioreqs1[] = {
{ ZD_CR10, 0x89 }, { ZD_CR15, 0x20 },
{ ZD_CR17, 0x2B }, /* for newest(3rd cut) AL2230 */
{ ZD_CR23, 0x40 }, { ZD_CR24, 0x20 }, { ZD_CR26, 0x93 },
{ ZD_CR28, 0x3e }, { ZD_CR29, 0x00 },
{ ZD_CR33, 0x28 }, /* 5621 */
{ ZD_CR34, 0x30 },
{ ZD_CR35, 0x3e }, /* for newest(3rd cut) AL2230 */
{ ZD_CR41, 0x24 }, { ZD_CR44, 0x32 },
{ ZD_CR46, 0x99 }, /* for newest(3rd cut) AL2230 */
{ ZD_CR47, 0x1e },
/* ZD1211B 05.06.10 */
{ ZD_CR48, 0x06 }, { ZD_CR49, 0xf9 }, { ZD_CR51, 0x01 },
{ ZD_CR52, 0x80 }, { ZD_CR53, 0x7e }, { ZD_CR65, 0x00 },
{ ZD_CR66, 0x00 }, { ZD_CR67, 0x00 }, { ZD_CR68, 0x00 },
{ ZD_CR69, 0x28 },
{ ZD_CR79, 0x58 }, { ZD_CR80, 0x30 }, { ZD_CR81, 0x30 },
{ ZD_CR87, 0x0a }, { ZD_CR89, 0x04 },
{ ZD_CR91, 0x00 }, /* 5621 */
{ ZD_CR92, 0x0a },
{ ZD_CR98, 0x8d }, /* 4804, for 1212 new algorithm */
{ ZD_CR99, 0x00 }, /* 5621 */
{ ZD_CR101, 0x13 }, { ZD_CR102, 0x27 },
{ ZD_CR106, 0x24 }, /* for newest(3rd cut) AL2230 */
{ ZD_CR107, 0x2a },
{ ZD_CR109, 0x13 }, /* 4804, for 1212 new algorithm */
{ ZD_CR110, 0x1f }, /* 4804, for 1212 new algorithm */
{ ZD_CR111, 0x1f }, { ZD_CR112, 0x1f }, { ZD_CR113, 0x27 },
{ ZD_CR114, 0x27 },
{ ZD_CR115, 0x26 }, /* 24->26 at 4902 for newest(3rd cut)
* AL2230
*/
{ ZD_CR116, 0x24 },
{ ZD_CR117, 0xfa }, /* for 1211b */
{ ZD_CR118, 0xfa }, /* for 1211b */
{ ZD_CR119, 0x10 },
{ ZD_CR120, 0x4f },
{ ZD_CR121, 0x6c }, /* for 1211b */
{ ZD_CR122, 0xfc }, /* E0->FC at 4902 */
{ ZD_CR123, 0x57 }, /* 5623 */
{ ZD_CR125, 0xad }, /* 4804, for 1212 new algorithm */
{ ZD_CR126, 0x6c }, /* 5614 */
{ ZD_CR127, 0x03 }, /* 4804, for 1212 new algorithm */
{ ZD_CR137, 0x50 }, /* 5614 */
{ ZD_CR138, 0xa8 },
{ ZD_CR144, 0xac }, /* 5621 */
{ ZD_CR150, 0x0d }, { ZD_CR252, 0x34 }, { ZD_CR253, 0x34 },
};
static const u32 rv1[] = {
0x8cccd0,
0x481dc0,
0xcfff00,
0x25a000,
};
static const u32 rv2[] = {
/* To improve AL2230 yield, improve phase noise, 4713 */
0x25a000,
0xa3b2f0,
0x6da010, /* Reg6 update for MP versio */
0xe36280, /* Modified by jxiao for Bor-Chin on 2004/08/02 */
0x116000,
0x9dc020, /* External control TX power (ZD_CR31) */
0x5ddb00, /* RegA update for MP version */
0xd99000, /* RegB update for MP version */
0x3ffbd0, /* RegC update for MP version */
0xb00000, /* RegD update for MP version */
/* improve phase noise and remove phase calibration,4713 */
0xf01a00,
};
static const struct zd_ioreq16 ioreqs2[] = {
{ ZD_CR251, 0x2f }, /* shdnb(PLL_ON)=0 */
{ ZD_CR251, 0x7f }, /* shdnb(PLL_ON)=1 */
};
static const u32 rv3[] = {
/* To improve AL2230 yield, 4713 */
0xf01b00,
0xf01e00,
0xf01a00,
};
static const struct zd_ioreq16 ioreqs3[] = {
/* related to 6M band edge patching, happens unconditionally */
{ ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
};
r = zd_iowrite16a_locked(chip, zd1211b_ioreqs_shared_1,
ARRAY_SIZE(zd1211b_ioreqs_shared_1));
if (r)
return r;
r = zd_iowrite16a_locked(chip, ioreqs1, ARRAY_SIZE(ioreqs1));
if (r)
return r;
if (IS_AL2230S(chip)) {
r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
ARRAY_SIZE(ioreqs_init_al2230s));
if (r)
return r;
}
r = zd_rfwritev_cr_locked(chip, zd1211b_al2230_table[0], 3);
if (r)
return r;
r = zd_rfwritev_cr_locked(chip, rv1, ARRAY_SIZE(rv1));
if (r)
return r;
if (IS_AL2230S(chip))
r = zd_rfwrite_locked(chip, 0x241000, RF_RV_BITS);
else
r = zd_rfwrite_locked(chip, 0x25a000, RF_RV_BITS);
if (r)
return r;
r = zd_rfwritev_cr_locked(chip, rv2, ARRAY_SIZE(rv2));
if (r)
return r;
r = zd_iowrite16a_locked(chip, ioreqs2, ARRAY_SIZE(ioreqs2));
if (r)
return r;
r = zd_rfwritev_cr_locked(chip, rv3, ARRAY_SIZE(rv3));
if (r)
return r;
r = zd_iowrite16a_locked(chip, ioreqs3, ARRAY_SIZE(ioreqs3));
if (r)
return r;
return zd1211b_al2230_finalize_rf(chip);
}
