EFI_STATUS
LcdPlatformGetVram (
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
OUT UINTN* VramSize
)
{
EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu;
UINTN MaxSize;
MaxSize = 0x500000;
*VramSize = MaxSize;
// Allocate VRAM from DRAM
Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES((MaxSize)), VramBaseAddress);
if (EFI_ERROR(Status)) {
return Status;
}
// Ensure the Cpu architectural protocol is already installed
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
// Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable.
Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);
if (EFI_ERROR(Status)) {
gBS->FreePool (VramBaseAddress);
return Status;
}
return EFI_SUCCESS;
}
EFI_STATUS
LcdPlatformGetVram (
OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,
OUT UINTN* VramSize
)
{
EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu;
Status = EFI_SUCCESS;
// Is it on the motherboard or on the daughterboard?
switch(PL111_CLCD_SITE) {
case ARM_VE_MOTHERBOARD_SITE:
*VramBaseAddress = (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOARD_BASE;
*VramSize = LCD_VRAM_SIZE;
break;
case ARM_VE_DAUGHTERBOARD_1_SITE:
*VramBaseAddress = (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE;
*VramSize = LCD_VRAM_SIZE;
// Allocate the VRAM from the DRAM so that nobody else uses it.
Status = gBS->AllocatePages( AllocateAddress, EfiBootServicesData, EFI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress);
if (EFI_ERROR(Status)) {
return Status;
}
// Ensure the Cpu architectural protocol is already installed
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
// Mark the VRAM as un-cachable. The VRAM is inside the DRAM, which is cachable.
Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);
ASSERT_EFI_ERROR(Status);
if (EFI_ERROR(Status)) {
gBS->FreePool(VramBaseAddress);
return Status;
}
break;
default:
// Unsupported site
Status = EFI_UNSUPPORTED;
break;
}
return Status;
}
/**
Initialize the state information for the CPU Architectural Protocol
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu;
// Make sure the Interrupt Controller Protocol is not already installed in the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
// Make sure all interrupts are disabled by default.
MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
NULL);
ASSERT_EFI_ERROR(Status);
//
// Get the CPU protocol that this driver requires.
//
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
//
// Unregister the default exception handler.
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
ASSERT_EFI_ERROR(Status);
//
// Register to receive interrupts
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
ASSERT_EFI_ERROR(Status);
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
ASSERT_EFI_ERROR(Status);
return Status;
}
STATIC
VOID
EFIAPI
CpuArchEventProtocolNotify (
IN EFI_EVENT Event,
IN VOID *Context
)
{
EFI_CPU_ARCH_PROTOCOL *Cpu;
EFI_STATUS Status;
//
// Get the CPU protocol that this driver requires.
//
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID**)&Cpu);
if (EFI_ERROR (Status)) {
return;
}
//
// Unregister the default exception handler.
//
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__, Status));
ASSERT (FALSE);
return;
}
//
// Register to receive interrupts
//
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, IrqInterruptHandler);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
__FUNCTION__, Status));
ASSERT (FALSE);
return;
}
}
VOID
WriteBootToOsPerformanceData (
VOID
)
/*++
Routine Description:
Allocates a block of memory and writes performance data of booting to OS into it.
Arguments:
None
Returns:
None
--*/
{
EFI_STATUS Status;
EFI_CPU_ARCH_PROTOCOL *Cpu;
EFI_PERFORMANCE_PROTOCOL *DrvPerf;
UINT32 mAcpiLowMemoryLength;
UINT32 LimitCount;
EFI_PERF_HEADER mPerfHeader;
EFI_PERF_DATA mPerfData;
EFI_GAUGE_DATA *DumpData;
EFI_HANDLE *Handles;
UINTN NoHandles;
UINT8 *Ptr;
UINT8 *PdbFileName;
UINT32 mIndex;
UINT64 Ticker;
UINT64 Freq;
UINT32 Duration;
UINT64 CurrentTicker;
UINT64 TimerPeriod;
//
// Retrive time stamp count as early as possilbe
//
Ticker = EfiReadTsc ();
//
// Get performance architecture protocol
//
Status = gBS->LocateProtocol (
&gEfiPerformanceProtocolGuid,
NULL,
&DrvPerf
);
if (EFI_ERROR (Status)) {
return ;
}
//
// Get CPU frequency
//
Status = gBS->LocateProtocol (
&gEfiCpuArchProtocolGuid,
NULL,
&Cpu
);
if (EFI_ERROR (Status)) {
return ;
}
//
// Get Cpu Frequency
//
Status = Cpu->GetTimerValue (Cpu, 0, &CurrentTicker, &TimerPeriod);
if (EFI_ERROR (Status)) {
return ;
}
//
// Put Detailed performance data into memory
//
Handles = NULL;
Status = gBS->LocateHandleBuffer (
AllHandles,
NULL,
NULL,
&NoHandles,
&Handles
);
if (EFI_ERROR (Status)) {
return ;
}
//
// Allocate a block of memory that contain performance data to OS
// if it is not allocated yet.
//
if (mAcpiLowMemoryBase == 0x0FFFFFFFF) {
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiReservedMemoryType,
4,
&mAcpiLowMemoryBase
);
if (EFI_ERROR (Status)) {
gBS->FreePool (Handles);
return ;
}
}
mAcpiLowMemoryLength = EFI_PAGES_TO_SIZE(4);
Ptr = (UINT8 *) ((UINT32) mAcpiLowMemoryBase + sizeof (EFI_PERF_HEADER));
LimitCount = (mAcpiLowMemoryLength - sizeof (EFI_PERF_HEADER)) / sizeof (EFI_PERF_DATA);
//
// Initialize performance data structure
//
EfiZeroMem (&mPerfHeader, sizeof (EFI_PERF_HEADER));
Freq = DivU64x32 (1000000000000, (UINTN) TimerPeriod, NULL);
mPerfHeader.CpuFreq = Freq;
//
// Record BDS raw performance data
//
mPerfHeader.BDSRaw = Ticker;
//
// Get DXE drivers performance
//
for (mIndex = 0; mIndex < NoHandles; mIndex++) {
Ticker = 0;
PdbFileName = NULL;
DumpData = DrvPerf->GetGauge (
DrvPerf, // Context
NULL, // Handle
NULL, // Token
NULL, // Host
NULL // PrecGauge
);
while (DumpData) {
if (DumpData->Handle == Handles[mIndex]) {
PdbFileName = &(DumpData->PdbFileName[0]);
if (DumpData->StartTick < DumpData->EndTick) {
Ticker += (DumpData->EndTick - DumpData->StartTick);
}
}
DumpData = DrvPerf->GetGauge (
DrvPerf, // Context
NULL, // Handle
NULL, // Token
NULL, // Host
DumpData // PrecGauge
);
}
Duration = (UINT32) DivU64x32 (
Ticker,
(UINT32) Freq,
NULL
);
if (Duration > 0) {
EfiZeroMem (&mPerfData, sizeof (EFI_PERF_DATA));
if (PdbFileName != NULL) {
EfiAsciiStrCpy (mPerfData.Token, PdbFileName);
}
mPerfData.Duration = Duration;
EfiCopyMem (Ptr, &mPerfData, sizeof (EFI_PERF_DATA));
Ptr += sizeof (EFI_PERF_DATA);
mPerfHeader.Count++;
if (mPerfHeader.Count == LimitCount) {
goto Done;
}
}
}
gBS->FreePool (Handles);
//
// Get inserted performance data
//
DumpData = DrvPerf->GetGauge (
DrvPerf, // Context
NULL, // Handle
NULL, // Token
NULL, // Host
NULL // PrecGauge
);
while (DumpData) {
if ((DumpData->Handle) || (DumpData->StartTick > DumpData->EndTick)) {
DumpData = DrvPerf->GetGauge (
DrvPerf, // Context
NULL, // Handle
NULL, // Token
NULL, // Host
DumpData // PrecGauge
);
continue;
}
EfiZeroMem (&mPerfData, sizeof (EFI_PERF_DATA));
ConvertChar16ToChar8 ((UINT8 *) mPerfData.Token, DumpData->Token);
mPerfData.Duration = (UINT32) DivU64x32 (
DumpData->EndTick - DumpData->StartTick,
(UINT32) Freq,
NULL
);
EfiCopyMem (Ptr, &mPerfData, sizeof (EFI_PERF_DATA));
Ptr += sizeof (EFI_PERF_DATA);
mPerfHeader.Count++;
if (mPerfHeader.Count == LimitCount) {
goto Done;
}
DumpData = DrvPerf->GetGauge (
DrvPerf, // Context
NULL, // Handle
NULL, // Token
NULL, // Host
DumpData // PrecGauge
);
}
Done:
mPerfHeader.Signiture = 0x66726550;
//
// Put performance data to memory
//
EfiCopyMem (
(UINTN *) (UINTN) mAcpiLowMemoryBase,
&mPerfHeader,
sizeof (EFI_PERF_HEADER)
);
gRT->SetVariable (
L"PerfDataMemAddr",
&gEfiGenericVariableGuid,
EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
sizeof (UINT32),
(VOID *) &mAcpiLowMemoryBase
);
return ;
}
/**
Initialize the state information for the CPU Architectural Protocol
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
EFI_CPU_ARCH_PROTOCOL *Cpu;
// Make sure the Interrupt Controller Protocol is not already installed in the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));
for (Index = 0; Index < mGicNumInterrupts; Index++) {
DisableInterruptSource (&gHardwareInterruptProtocol, Index);
// Set Priority
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
~(0xff << RegShift),
ARM_GIC_DEFAULT_PRIORITY << RegShift
);
}
// Configure interrupts for cpu 0
for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), 0x01010101);
}
// Set binary point reg to 0x7 (no preemption)
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
// Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
// Enable gic cpu interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
// Enable gic distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
// Initialize the array for the Interrupt Handlers
gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
Status = gBS->InstallMultipleProtocolInterfaces (
&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
NULL
);
ASSERT_EFI_ERROR (Status);
//
// Get the CPU protocol that this driver requires.
//
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
//
// Unregister the default exception handler.
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
ASSERT_EFI_ERROR(Status);
//
// Register to receive interrupts
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
ASSERT_EFI_ERROR(Status);
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
ASSERT_EFI_ERROR (Status);
return Status;
}
VOID
EFIAPI
PlatformConfigOnSmmConfigurationProtocol (
IN EFI_EVENT Event,
IN VOID *Context
)
/*++
Routine Description:
Function runs in PI-DXE to perform platform specific config when
SmmConfigurationProtocol is installed.
Arguments:
Event - The event that occured.
Context - For EFI compatiblity. Not used.
Returns:
None.
--*/
{
EFI_STATUS Status;
UINT32 NewValue;
UINT64 BaseAddress;
UINT64 SmramLength;
EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol; // RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE
VOID *SmmCfgProt;
Status = gBS->LocateProtocol (&gEfiSmmConfigurationProtocolGuid, NULL, &SmmCfgProt);
if (Status != EFI_SUCCESS){
DEBUG ((DEBUG_INFO, "gEfiSmmConfigurationProtocolGuid triggered but not valid.\n"));
return;
}
if (mMemCfgDone) {
DEBUG ((DEBUG_INFO, "Platform DXE Mem config already done.\n"));
return;
}
//
// Disable eSram block (this will also clear/zero eSRAM)
// We only use eSRAM in the PEI phase. Disable now that we are in the DXE phase
//
NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK);
NewValue |= BLOCK_DISABLE_PG;
QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK, NewValue);
//
// Update HMBOUND to top of DDR3 memory and LOCK
// We disabled eSRAM so now we move HMBOUND down to top of DDR3
//
QNCGetTSEGMemoryRange (&BaseAddress, &SmramLength);
NewValue = (UINT32)(BaseAddress + SmramLength);
DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue));
QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK));
if(FeaturePcdGet (PcdEnableSecureLock)) {
//
// Lock IMR5 now that HMBOUND is locked (legacy S3 region)
//
NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL);
NewValue |= IMR_LOCK;
QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);
//
// Lock IMR6 now that HMBOUND is locked (ACPI Reclaim/ACPI/Runtime services/Reserved)
//
NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL);
NewValue |= IMR_LOCK;
QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);
//
// Disable IMR2 memory protection (RMU Main Binary)
//
QncImrWrite (
QUARK_NC_MEMORY_MANAGER_IMR2,
(UINT32)(IMRL_RESET & ~IMR_EN),
(UINT32)IMRH_RESET,
(UINT32)IMRX_ALL_ACCESS,
(UINT32)IMRX_ALL_ACCESS
);
//
// Disable IMR3 memory protection (Default SMRAM)
//
QncImrWrite (
QUARK_NC_MEMORY_MANAGER_IMR3,
(UINT32)(IMRL_RESET & ~IMR_EN),
(UINT32)IMRH_RESET,
(UINT32)IMRX_ALL_ACCESS,
(UINT32)IMRX_ALL_ACCESS
);
//
// Disable IMR4 memory protection (eSRAM).
//
QncImrWrite (
QUARK_NC_MEMORY_MANAGER_IMR4,
(UINT32)(IMRL_RESET & ~IMR_EN),
(UINT32)IMRH_RESET,
(UINT32)IMRX_ALL_ACCESS,
(UINT32)IMRX_ALL_ACCESS
);
}
//
// RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE
// Workaround to make default SMRAM UnCachable
//
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **) &CpuArchProtocol);
ASSERT_EFI_ERROR (Status);
CpuArchProtocol->SetMemoryAttributes (
CpuArchProtocol,
(EFI_PHYSICAL_ADDRESS) SMM_DEFAULT_SMBASE,
SMM_DEFAULT_SMBASE_SIZE_BYTES,
EFI_MEMORY_WB
);
mMemCfgDone = TRUE;
}
/**
Initialize the state information for the CPU Architectural Protocol
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
InterruptDxeInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
UINTN Index;
UINT32 RegOffset;
UINTN RegShift;
EFI_CPU_ARCH_PROTOCOL *Cpu;
UINT32 CpuTarget;
// Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
DEBUG_CODE_BEGIN();
if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
}
DEBUG_CODE_END();
// Make sure the Interrupt Controller Protocol is not already installed in the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));
mGicNumInterrupts /=8;
for (Index = 0; Index < mGicNumInterrupts; Index++) {
(VOID)DisableInterruptSource (&gHardwareInterruptProtocol, Index);
// Set Priority
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
~(UINT32)(0xff << RegShift),
ARM_GIC_DEFAULT_PRIORITY << RegShift
);
}
// Configure interrupts for Primary Cpu
CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
CpuTarget |= CpuTarget << 16;
for (Index = 0; Index < (mGicNumInterrupts / 2); Index++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
}
//end_d00183345, 2012-11-17
// Set binary point reg to 0x7 (no preemption)
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x3);
// Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
// Enable gic cpu interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
// Enable gic distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x7);
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISR, ~0);
//MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISR, ~0);
// Initialize the array for the Interrupt Handlers
gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
Status = gBS->InstallMultipleProtocolInterfaces (
&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
NULL
);
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status))
{
//for fortify
return Status;
}
//
// Get the CPU protocol that this driver requires.
//
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
ASSERT_EFI_ERROR(Status);
if (EFI_ERROR (Status))
{
//for fortify
return Status;
}
//
// Unregister the default exception handler.
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_AARCH64_IRQ, NULL);
ASSERT_EFI_ERROR(Status);
if (EFI_ERROR (Status))
{
//for fortify
return Status;
}
//
// Register to receive interrupts
//
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_AARCH64_IRQ, IrqInterruptHandler);
ASSERT_EFI_ERROR(Status);
if (EFI_ERROR (Status))
{
//for fortify
return Status;
}
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status))
{
//for fortify
return Status;
}
return Status;
}
