bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) { auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { EM.insert(std::make_pair(DstR, SrcR)); }; unsigned Opc = MI->getOpcode(); switch (Opc) { case Hexagon::A2_combinew: { const MachineOperand &DstOp = MI->getOperand(0); const MachineOperand &HiOp = MI->getOperand(1); const MachineOperand &LoOp = MI->getOperand(2); assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); mapRegs({ DstOp.getReg(), Hexagon::subreg_hireg }, { HiOp.getReg(), HiOp.getSubReg() }); mapRegs({ DstOp.getReg(), Hexagon::subreg_loreg }, { LoOp.getReg(), LoOp.getSubReg() }); return true; } case Hexagon::A2_addi: { const MachineOperand &A = MI->getOperand(2); if (!A.isImm() || A.getImm() != 0) return false; } // Fall through. case Hexagon::A2_tfr: { const MachineOperand &DstOp = MI->getOperand(0); const MachineOperand &SrcOp = MI->getOperand(1); mapRegs({ DstOp.getReg(), DstOp.getSubReg() }, { SrcOp.getReg(), SrcOp.getSubReg() }); return true; } } return CopyPropagation::interpretAsCopy(MI, EM); }
bool CopyPropagation::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) { unsigned Opc = MI->getOpcode(); switch (Opc) { case TargetOpcode::COPY: { const MachineOperand &Dst = MI->getOperand(0); const MachineOperand &Src = MI->getOperand(1); RegisterRef DstR = { Dst.getReg(), Dst.getSubReg() }; RegisterRef SrcR = { Src.getReg(), Src.getSubReg() }; if (TargetRegisterInfo::isVirtualRegister(DstR.Reg)) { if (!TargetRegisterInfo::isVirtualRegister(SrcR.Reg)) return false; MachineRegisterInfo &MRI = DFG.getMF().getRegInfo(); if (MRI.getRegClass(DstR.Reg) != MRI.getRegClass(SrcR.Reg)) return false; } else if (TargetRegisterInfo::isPhysicalRegister(DstR.Reg)) { if (!TargetRegisterInfo::isPhysicalRegister(SrcR.Reg)) return false; const TargetRegisterInfo &TRI = DFG.getTRI(); if (TRI.getMinimalPhysRegClass(DstR.Reg) != TRI.getMinimalPhysRegClass(SrcR.Reg)) return false; } else { // Copy between some unknown objects. return false; } EM.insert(std::make_pair(DstR, SrcR)); return true; } case TargetOpcode::REG_SEQUENCE: { const MachineOperand &Dst = MI->getOperand(0); RegisterRef DefR = { Dst.getReg(), Dst.getSubReg() }; SmallVector<TargetInstrInfo::RegSubRegPairAndIdx,2> Inputs; const TargetInstrInfo &TII = DFG.getTII(); if (!TII.getRegSequenceInputs(*MI, 0, Inputs)) return false; for (auto I : Inputs) { unsigned S = DFG.getTRI().composeSubRegIndices(DefR.Sub, I.SubIdx); RegisterRef DR = { DefR.Reg, S }; RegisterRef SR = { I.Reg, I.SubReg }; EM.insert(std::make_pair(DR, SR)); } return true; } } return false; }
bool CopyPropagation::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) { unsigned Opc = MI->getOpcode(); switch (Opc) { case TargetOpcode::COPY: { const MachineOperand &Dst = MI->getOperand(0); const MachineOperand &Src = MI->getOperand(1); RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); assert(TargetRegisterInfo::isPhysicalRegister(DstR.Reg)); assert(TargetRegisterInfo::isPhysicalRegister(SrcR.Reg)); const TargetRegisterInfo &TRI = DFG.getTRI(); if (TRI.getMinimalPhysRegClass(DstR.Reg) != TRI.getMinimalPhysRegClass(SrcR.Reg)) return false; EM.insert(std::make_pair(DstR, SrcR)); return true; } case TargetOpcode::REG_SEQUENCE: llvm_unreachable("Unexpected REG_SEQUENCE"); } return false; }
bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) { auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { EM.insert(std::make_pair(DstR, SrcR)); }; DataFlowGraph &DFG = getDFG(); unsigned Opc = MI->getOpcode(); switch (Opc) { case Hexagon::A2_combinew: { const MachineOperand &DstOp = MI->getOperand(0); const MachineOperand &HiOp = MI->getOperand(1); const MachineOperand &LoOp = MI->getOperand(2); assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi), DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo), DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); return true; } case Hexagon::A2_addi: { const MachineOperand &A = MI->getOperand(2); if (!A.isImm() || A.getImm() != 0) return false; LLVM_FALLTHROUGH; } case Hexagon::A2_tfr: { const MachineOperand &DstOp = MI->getOperand(0); const MachineOperand &SrcOp = MI->getOperand(1); mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); return true; } } return CopyPropagation::interpretAsCopy(MI, EM); }