errlHndl_t call_mss_eff_grouping(IStepError & io_istepErr)
{
errlHndl_t l_err = nullptr;
TARGETING::TargetHandleList l_procsList;
getAllChips(l_procsList, TYPE_PROC);
for (const auto & l_cpu_target : l_procsList)
{
// print call to hwp and write HUID of the target(s)
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"p9_mss_eff_grouping HWP cpu target HUID %.8X",
TARGETING::get_huid(l_cpu_target));
// cast OUR type of target to a FAPI type of target.
const fapi2::Target <fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_cpu_target
(l_cpu_target);
FAPI_INVOKE_HWP(l_err, p9_mss_eff_grouping, l_fapi_cpu_target);
// process return code.
if ( l_err )
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"ERROR 0x%.8X: p9_mss_eff_grouping HWP on target %.8x",
l_err->reasonCode(), TARGETING::get_huid(l_cpu_target));
// capture the target data in the elog
ErrlUserDetailsTarget(l_cpu_target).addToLog(l_err);
io_istepErr.addErrorDetails(l_err);
errlCommit(l_err, ISTEP_COMP_ID);
}
else
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"SUCCESS : p9_mss_eff_grouping HWP on target %.8x",
TARGETING::get_huid(l_cpu_target));
}
} // end processor list processing
return l_err;
}
/**
* @brief Check flash image SHA512 hash value of each explorer chip
* and update the flash if it does not match the SHA512 hash
* of the image in PNOR.
*
* @param[out] o_stepError Error handle for logging istep failures
*
*/
void updateAll(IStepError& o_stepError)
{
bool l_imageLoaded = false;
errlHndl_t l_err = nullptr;
bool l_rebootRequired = false;
// Get a list of OCMB chips
TARGETING::TargetHandleList l_ocmbTargetList;
getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP);
TRACFCOMP(g_trac_expupd, ENTER_MRK
"updateAll: %d ocmb chips found",
l_ocmbTargetList.size());
do
{
// If no OCMB chips exist, we're done.
if(l_ocmbTargetList.size() == 0)
{
break;
}
// Read explorer fw image from pnor
PNOR::SectionInfo_t l_pnorSectionInfo;
rawImageInfo_t l_imageInfo;
#ifdef CONFIG_SECUREBOOT
l_err = PNOR::loadSecureSection(PNOR::OCMBFW);
if(l_err)
{
TRACFCOMP(g_trac_expupd, ERR_MRK
"updateAll: Failed to load OCMBFW section"
" from PNOR!");
l_err->collectTrace(EXPUPD_COMP_NAME);
// Create IStep error log and cross reference to error that occurred
o_stepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, EXPUPD_COMP_ID );
break;
}
#endif //CONFIG_SECUREBOOT
l_imageLoaded = true;
// get address and size of packaged image
l_err = PNOR::getSectionInfo(PNOR::OCMBFW, l_pnorSectionInfo);
if(l_err)
{
TRACFCOMP(g_trac_expupd, ERR_MRK
"updateAll: Failure in getSectionInfo()");
l_err->collectTrace(EXPUPD_COMP_NAME);
// Create IStep error log and cross reference to error that occurred
o_stepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, EXPUPD_COMP_ID );
break;
}
// Verify the header and retrieve address, size and
// SHA512 hash of unpackaged image
l_err = ocmbFwValidateImage(
l_pnorSectionInfo.vaddr,
l_pnorSectionInfo.secureProtectedPayloadSize,
l_imageInfo);
if(l_err)
{
TRACFCOMP(g_trac_expupd, ERR_MRK
"updateAll: Failure in expupdValidateImage");
l_err->collectTrace(EXPUPD_COMP_NAME);
// Create IStep error log and cross reference to error that occurred
o_stepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, EXPUPD_COMP_ID );
break;
}
// For each explorer chip, compare flash hash with PNOR hash and
// create a list of explorer chips with differing hash values.
TARGETING::TargetHandleList l_flashUpdateList;
for(const auto & l_ocmbTarget : l_ocmbTargetList)
{
sha512regs_t l_regs;
//skip all gemini ocmb chips (not updateable)
if(l_ocmbTarget->getAttr<TARGETING::ATTR_CHIP_ID>() ==
POWER_CHIPID::GEMINI_16)
{
TRACFCOMP(g_trac_expupd,
"updateAll: skipping update of gemini OCMB 0x%08x",
TARGETING::get_huid(l_ocmbTarget));
continue;
}
//retrieve the SHA512 hash for the currently flashed image.
l_err = getFlashedHash(l_ocmbTarget, l_regs);
if(l_err)
{
TRACFCOMP(g_trac_expupd, ERR_MRK
"updateAll: Failure in getFlashedHash(huid = 0x%08x)",
TARGETING::get_huid(l_ocmbTarget));
l_err->collectTrace(EXPUPD_COMP_NAME);
// Create IStep error log and cross reference to error
// that occurred
o_stepError.addErrorDetails(l_err);
errlCommit(l_err, EXPUPD_COMP_ID);
//Don't stop on error, go to next target.
continue;
}
// Trace the hash and image ID values
TRACFCOMP(g_trac_expupd,
"updateAll: OCMB 0x%08x image ID=0x%08x",
TARGETING::get_huid(l_ocmbTarget), l_regs.imageId);
TRACFBIN(g_trac_expupd, "SHA512 HASH FROM EXPLORER",
l_regs.sha512Hash, HEADER_SHA512_SIZE);
//Compare hashes. If different, add to list for update.
if(memcmp(l_regs.sha512Hash, l_imageInfo.imageSHA512HashPtr,
HEADER_SHA512_SIZE))
{
TRACFCOMP(g_trac_expupd,
"updateAll: SHA512 hash mismatch on ocmb[0x%08x]",
TARGETING::get_huid(l_ocmbTarget));
//add target to our list of targets needing an update
l_flashUpdateList.push_back(l_ocmbTarget);
}
else
{
TRACFCOMP(g_trac_expupd,
"updateAll: SHA512 hash for ocmb[0x%08x]"
" matches SHA512 hash of PNOR image.",
TARGETING::get_huid(l_ocmbTarget));
}
}
TRACFCOMP(g_trac_expupd,
"updateAll: updating flash for %d OCMB chips",
l_flashUpdateList.size());
// update each explorer in the list of chips needing updates
for(const auto & l_ocmb : l_flashUpdateList)
{
TRACFCOMP(g_trac_expupd, "updateAll: updating OCMB 0x%08x",
TARGETING::get_huid(l_ocmb));
fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>l_fapi2Target(l_ocmb);
// reset watchdog for each ocmb as this function can be very slow
INITSERVICE::sendProgressCode();
// Invoke procedure
FAPI_INVOKE_HWP(l_err, exp_fw_update, l_fapi2Target,
l_imageInfo.imagePtr, l_imageInfo.imageSize);
if (l_err)
{
TRACFCOMP(g_trac_expupd,
"Error from exp_fw_update for OCMB 0x%08x",
TARGETING::get_huid(l_ocmb));
l_err->collectTrace(EXPUPD_COMP_NAME);
// Create IStep error log and cross reference to error
// that occurred
o_stepError.addErrorDetails( l_err );
errlCommit(l_err, EXPUPD_COMP_ID);
// Don't stop on error, go to next target.
continue;
}
else
{
TRACFCOMP(g_trac_expupd,
"updateAll: successfully updated OCMB 0x%08x",
TARGETING::get_huid(l_ocmb));
// Request reboot for new firmware to be used
l_rebootRequired = true;
}
}
}while(0);
// unload explorer fw image
if(l_imageLoaded)
{
#ifdef CONFIG_SECUREBOOT
l_err = PNOR::unloadSecureSection(PNOR::OCMBFW);
if(l_err)
{
TRACFCOMP(g_trac_expupd, ERR_MRK
"updateAll: Failed to unload OCMBFW");
l_err->collectTrace(EXPUPD_COMP_NAME);
// Create IStep error log and cross reference to error that occurred
o_stepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, EXPUPD_COMP_ID );
}
#endif //CONFIG_SECUREBOOT
}
// force reboot if any updates were successful
if(l_rebootRequired)
{
TRACFCOMP(g_trac_expupd,
"updateAll: OCMB chip(s) was updated. Requesting reboot...");
Target* l_pTopLevel = nullptr;
targetService().getTopLevelTarget( l_pTopLevel );
assert(l_pTopLevel, "expupd::updateAll: no TopLevelTarget");
auto l_reconfigAttr =
l_pTopLevel->getAttr<TARGETING::ATTR_RECONFIGURE_LOOP>();
l_reconfigAttr |= RECONFIGURE_LOOP_OCMB_FW_UPDATE;
l_pTopLevel->setAttr<TARGETING::ATTR_RECONFIGURE_LOOP>(l_reconfigAttr);
}
else
{
TRACFCOMP(g_trac_expupd, "updateAll: No OCMB chips were updated");
}
TRACFCOMP(g_trac_expupd, EXIT_MRK"updateAll()");
}
//
// Wrapper function to call mss_post_draminit
//
void mss_post_draminit( IStepError & l_stepError )
{
errlHndl_t l_err = NULL;
bool rerun_vddr = false;
do {
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "mss_post_draminit entry" );
set_eff_config_attrs_helper(MC_CONFIG::POST_DRAM_INIT, rerun_vddr);
if ( rerun_vddr == false )
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"mss_post_draminit: nothing to do" );
break;
}
// Call mss_volt_vddr_offset to recalculate VDDR voltage
l_err = MC_CONFIG::setMemoryVoltageDomainOffsetVoltage<
TARGETING::ATTR_MSS_VOLT_VDDR_OFFSET_DISABLE,
TARGETING::ATTR_MEM_VDDR_OFFSET_MILLIVOLTS,
TARGETING::ATTR_VMEM_ID>();
if(l_err)
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "mss_post_draminit: "
"ERROR 0x%08X: setMemoryVoltageDomainOffsetVoltage for VDDR domain",
l_err->reasonCode());
l_stepError.addErrorDetails(l_err);
errlCommit(l_err,HWPF_COMP_ID);
break;
}
else
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"mss_post_draminit: mss_volt_vddr_offset(): SUCCESS");
}
// Call HWSV to call POWR code
// This fuction has compile-time binding for different platforms
l_err = platform_adjust_vddr_post_dram_init();
if( l_err )
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"ERROR 0x%.8X: mss_post_draminit: "
"platform_adjust_vddr_post_dram_init() returns error",
l_err->reasonCode());
// Create IStep error log and cross reference to error that occurred
l_stepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, HWPF_COMP_ID );
}
} while(0);
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"mss_post_draminit exit" );
return;
}
void axone_dccal_setup(IStepError & io_istepError)
{
errlHndl_t l_err = nullptr;
TargetHandleList l_omic_target_list;
getAllChiplets(l_omic_target_list, TYPE_OMIC);
for (const auto & l_omic_target : l_omic_target_list)
{
// call the HWP with each target
fapi2::Target<fapi2::TARGET_TYPE_OMIC> l_fapi_omic_target
(l_omic_target);
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"p9a_io_omi_scominit HWP target HUID %.8x",
get_huid(l_omic_target));
FAPI_INVOKE_HWP(l_err, p9a_io_omi_scominit, l_fapi_omic_target);
// process return code.
if ( l_err )
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"ERROR 0x%.8X: p9a_io_omi_scominit HWP on target HUID %.8x",
l_err->reasonCode(), TARGETING::get_huid(l_omic_target) );
// capture the target data in the elog
ErrlUserDetailsTarget(l_omic_target).addToLog( l_err );
// Create IStep error log and cross reference to error that occurred
io_istepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, ISTEP_COMP_ID );
}
else
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"SUCCESS : p9a_io_omi_scominit HWP on target HUID %.8x",
TARGETING::get_huid(l_omic_target) );
}
TargetHandleList l_omi_target_list;
getChildOmiTargetsByState(l_omi_target_list,
l_omic_target,
CLASS_UNIT,
TYPE_OMI,
UTIL_FILTER_FUNCTIONAL);
uint32_t l_laneVector = 0x00000000;
for(const auto & l_omi_target : l_omi_target_list)
{
// The OMI dc calibration HWP requires us to pass in the OMIC target
// and then a bit mask representing which positon of OMI we are calibrating.
// To get the position of the OMI relative to its parent OMIC, look up
// ATTR_OMI_DL_GROUP_POS then shift the POS_0_VECTOR = 0x000000FF by 1 byte to the left
// for every position away from 0 OMI_DL_GROUP_POS is.
// Therefore
// POS_0_VECTOR = 0x000000FF
// POS_1_VECTOR = 0x0000FF00
// POS_2_VECTOR = 0x00FF0000
l_laneVector |=
POS_0_VECTOR << (l_omi_target->getAttr<ATTR_OMI_DL_GROUP_POS>() * BITS_PER_BYTE);
}
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"p9a_io_omi_dccal HWP target HUID %.8x with lane vector 0x%x",
TARGETING::get_huid(l_omic_target), l_laneVector);
FAPI_INVOKE_HWP(l_err, p9a_io_omi_dccal, l_fapi_omic_target, l_laneVector);
// process return code.
if ( l_err )
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"ERROR 0x%.8X: p9a_io_omi_dccal HWP on target HUID %.8x with lane vector 0x%x",
l_err->reasonCode(), TARGETING::get_huid(l_omic_target), l_laneVector);
// capture the target data in the elog
ErrlUserDetailsTarget(l_omic_target).addToLog( l_err );
l_err->collectTrace("ISTEPS_TRACE", 256);
// Create IStep error log and cross reference to error that occurred
io_istepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, ISTEP_COMP_ID );
}
else
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
"SUCCESS : p9a_io_omi_dccal HWP on target HUID %.8x with lane vector 0x%x",
TARGETING::get_huid(l_omic_target), l_laneVector );
}
}
}
void cumulus_dccal_setup(IStepError & io_istepError)
{
errlHndl_t l_err = nullptr;
TARGETING::TargetHandleList l_procTargetList;
getAllChips(l_procTargetList, TYPE_PROC);
for (const auto & l_proc_target : l_procTargetList)
{
// a. p9_io_dmi_dccal.C (DMI target)
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"p9_io_dmi_dccal HWP target HUID %.8x",
TARGETING::get_huid(l_proc_target));
// call the HWP with each target
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target
(l_proc_target);
FAPI_INVOKE_HWP(l_err, p9_io_dmi_dccal, l_fapi_proc_target);
// process return code.
if ( l_err )
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"ERROR 0x%.8X: p9_io_dmi_dccal HWP on target HUID %.8x",
l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
// capture the target data in the elog
ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
// Create IStep error log and cross reference to error that occurred
io_istepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, ISTEP_COMP_ID );
}
else
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"SUCCESS : p9_io_dmi_dccal HWP on target HUID %.8x",
TARGETING::get_huid(l_proc_target) );
}
// b. p9_io_cen_dccal.C (Centaur target)
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"p9_io_cen_dccal HWP target HUID %.8x",
TARGETING::get_huid(l_proc_target));
FAPI_INVOKE_HWP(l_err, p9_io_cen_dccal, l_fapi_proc_target);
// process return code.
if ( l_err )
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"ERROR 0x%.8X: p9_io_cen_dccal HWP on target HUID %.8x",
l_err->reasonCode(), TARGETING::get_huid(l_proc_target) );
// capture the target data in the elog
ErrlUserDetailsTarget(l_proc_target).addToLog( l_err );
// Create IStep error log and cross reference to error that occurred
io_istepError.addErrorDetails( l_err );
// Commit Error
errlCommit( l_err, ISTEP_COMP_ID );
}
else
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"SUCCESS : p9_io_cen_dccal HWP on target HUID %.8x",
TARGETING::get_huid(l_proc_target) );
}
}
}
