/**
*
* This function handle errors occur in memory code.
*
*
* @param[in,out] *MCTPtr - pointer to DIE_STRUCT.
* @param[in,out] DCT - DCT that needs to be handled.
* @param[in,out] ChipSelMask - Chip select mask that needs to be handled
* @param[in,out] *StdHeader - pointer to AMD_CONFIG_PARAMS
*
* @return TRUE - No fatal error occurs.
* @return FALSE - Fatal error occurs.
*/
BOOLEAN
MemErrHandle (
IN DIE_STRUCT *MCTPtr,
IN UINT8 DCT,
IN UINT16 ChipSelMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN ErrorRecovery;
BOOLEAN IgnoreErr;
DCT_STRUCT *DCTPtr;
UINT8 CurrentDCT;
LOCATE_HEAP_PTR LocHeap;
MEM_NB_BLOCK *NBPtr;
MEM_MAIN_DATA_BLOCK mmData;
DCTPtr = MCTPtr->DctData;
ErrorRecovery = TRUE;
IgnoreErr = FALSE;
IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, StdHeader);
if (ErrorRecovery) {
if (DCT == EXCLUDE_ALL_DCT) {
// Exclude all DCTs on a node
for (CurrentDCT = 0; CurrentDCT < MCTPtr->DctCount; CurrentDCT++) {
DCTPtr[CurrentDCT].Timings.CsTestFail = DCTPtr[CurrentDCT].Timings.CsPresent;
}
} else if (ChipSelMask == EXCLUDE_ALL_CHIPSEL) {
// Exclude the specified DCT
DCTPtr[DCT].Timings.CsTestFail = DCTPtr[DCT].Timings.CsPresent;
} else {
// Exclude the chip select that has been marked out
DCTPtr[DCT].Timings.CsTestFail |= ChipSelMask & DCTPtr[DCT].Timings.CsPresent;
IDS_OPTION_HOOK (IDS_LOADCARD_ERROR_RECOVERY, &DCTPtr[DCT], StdHeader);
}
// Exclude the failed dimm to recovery from error
if (MCTPtr->NodeMemSize != 0) {
LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
// NB block has already been constructed by main block.
// No need to construct it here.
NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
if (!NBPtr->SharedPtr->NodeMap[MCTPtr->NodeId].IsValid) {
// Memory map has not been calculated, no need to remap memory across node here.
// Only need to remap memory within the node.
NBPtr = &NBPtr[MCTPtr->NodeId];
NBPtr->FeatPtr->ExcludeDIMM (NBPtr);
} else {
// Need to remap memory across the whole system.
mmData.MemPtr = NBPtr->MemPtr;
mmData.mmSharedPtr = NBPtr->SharedPtr;
mmData.NBPtr = NBPtr;
mmData.TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[NBPtr->MemPtr->DieCount]);
mmData.DieCount = NBPtr->MemPtr->DieCount;
if (!MemFeatMain.ExcludeDIMM (&mmData)) {
return FALSE;
}
}
}
// If allocation fails, that means the code is not running at BSP.
// Parallel training is in process.
// Remap for parallel training will be done when control returns to BSP.
}
return TRUE;
} else {
IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, StdHeader);
if (IgnoreErr) {
return TRUE;
}
SetMemError (AGESA_FATAL, MCTPtr);
ASSERT(FALSE); // ErrorRecovery is FALSE
return FALSE;
}
}
/**
*
*
* This function defines the memory initialization flow for
* systems that only support RB processors.
*
* @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
*
* @return AGESA_STATUS
* - AGESA_ALERT
* - AGESA_FATAL
* - AGESA_SUCCESS
* - AGESA_WARNING
*/
AGESA_STATUS
MemMFlowDA (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
)
{
UINT8 Node;
UINT8 NodeCnt;
MEM_NB_BLOCK *NBPtr;
MEM_TECH_BLOCK *TechPtr;
NBPtr = MemMainPtr->NBPtr;
TechPtr = MemMainPtr->TechPtr;
NodeCnt = MemMainPtr->DieCount;
//----------------------------------------------------------------
// Initialize MCT
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// Low voltage DDR3
//----------------------------------------------------------------
// Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Initialize DRAM and DCTs, and Create Memory Map
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
// Initialize Memory Controller and Dram
IDS_HDT_CONSOLE ("!Node %d\n", Node);
if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
return AGESA_FATAL; // fatalexit
}
// Create memory map
AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------
// If there is no dimm on the system, do fatal exit
//----------------------------------------------------
if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
ASSERT (FALSE);
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Synchronize DCTs
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// CpuMemTyping
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Before Training Table values
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
}
//----------------------------------------------------------------
// Memory Context Restore
//----------------------------------------------------------------
if (!MemFeatMain.MemRestore (MemMainPtr)) {
// Do DQS training only if memory context restore fails
//----------------------------------------------------------------
// Training
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
IDS_OPTION_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader));
MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
if (!MemFeatMain.Training (MemMainPtr)) {
return AGESA_FATAL;
}
IDS_HDT_CONSOLE ("\nEnd DQS training\n\n");
}
//----------------------------------------------------------------
// Disable chipselects that fail training
//----------------------------------------------------------------
MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
MemFeatMain.ExcludeDIMM (MemMainPtr);
MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
//----------------------------------------------------------------
// OtherTiming
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// After Training Table values
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
}
//----------------------------------------------------------------
// SetDqsEccTimings
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// Online Spare
//----------------------------------------------------------------
if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Interleave banks
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
return AGESA_FATAL;
}
}
}
//----------------------------------------------------------------
// Interleave Nodes
//----------------------------------------------------------------
if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Interleave channels
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
return AGESA_FATAL;
}
}
}
//----------------------------------------------------------------
// UMA Allocation & UMAMemTyping
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Interleave region
//----------------------------------------------------------------
NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
//----------------------------------------------------------------
// ECC
//----------------------------------------------------------------
if (!MemFeatMain.InitEcc (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Memory Clear
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
if (!MemFeatMain.MemClr (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// OnDimm Thermal
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
return AGESA_FATAL;
}
}
}
//----------------------------------------------------------------
// Finalize MCT
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// Memory Context Save
//----------------------------------------------------------------
MemFeatMain.MemSave (MemMainPtr);
//----------------------------------------------------------------
// Memory DMI support
//----------------------------------------------------------------
if (!MemFeatMain.MemDmi (MemMainPtr)) {
return AGESA_CRITICAL;
}
return AGESA_SUCCESS;
}