void Operator::outputVHDLEntity(std::ostream& o) {
unsigned int i;
if(isSequential() && getClkName().compare("") == 0) {
std::cerr << "-- Can't find clock port for sequential component" << std::endl;
}
o << "entity " << uniqueName_ << " is" << endl;
if (ioList_.size() > 0)
{
o << tab << "port ( " << endl;
/*
if(isSequential()) {
o << getClkName() << " : in std_logic;" <<endl;
std::string rst = getRstName();
if (rst.compare("") != 0) {
o << rst << " : in std_logic;" <<endl;
}
}
*/
for (i=0; i<this->ioList_.size(); i++){
Signal* s = this->ioList_[i];
// if (i>0 || isSequential()) // align signal names
// o<<" ";
o<< tab << tab << tab << s->toVHDL();
if(i < this->ioList_.size()-1) o<<";" << endl;
}
o << endl << tab << ");"<<endl;
}
o << "end entity;" << endl << endl;
}
void Operator::outputVHDLSignalDeclarations(std::ostream& o) {
for (unsigned int i=0; i < this->signalList_.size(); i++){
Signal* s = this->signalList_[i];
o<<tab<< s->toVHDL() << ";" << endl;
}
}