//-----------------------------------------------------------------------------
fapi::ReturnCode
Bus::operation(Transaction& trans)
{
fapi::ReturnCode rc;
Slave* slave= 0;
do
{
for( slave = iv_primarySlaves; slave; slave = slave->iv_next )
{
if( (trans.iv_address >= slave->iv_base) && (trans.iv_address < (slave->iv_base + slave->iv_size) ) )
{
break; // found a primary slave
}
}
if( slave == 0 )
{ // primary slaves did not hold the transaction address. Try using the secondary slaves.
for( slave = iv_secondarySlaves; slave; slave = slave->iv_next )
{
if( (trans.iv_address >= slave->iv_base) && (trans.iv_address < (slave->iv_base + slave->iv_size) ) )
{
break; // found a secondary slave
}
}
}
break;
}while(1);
do
{
if( slave == 0 ) // neither primary nor secondary slaves held the address
{
trans.busError(ME_NOT_MAPPED_ON_BUS);
FAPI_ERR("No bus slave claimed address 0x%08x\n", trans.iv_address);
FAPI_SET_HWP_ERROR(rc, RC_POREVE_PORE_NOT_MAPPED_ON_BUS);
break;
}
if( (trans.iv_mode & slave->iv_permissions) == 0 ){
FAPI_ERR("Access denied for address 0x%08x, "
"mode = %d, slave permissions = %d\n",
trans.iv_address, trans.iv_mode, slave->iv_permissions);
trans.busError(ME_BUS_SLAVE_PERMISSION_DENIED);
FAPI_SET_HWP_ERROR(rc, RC_POREVE_BUS_SLAVE_PERMISSION_DENIED);
break;
}
trans.iv_offset = trans.iv_address - slave->iv_base;
rc = slave->operation( trans );
break;
}while(1);
return rc;
}
//-----------------------------------------------------------------------------
fapi::ReturnCode
OciSlave::operation(Transaction& io_transaction)
{
fapi::ReturnCode rc;
ModelError me;
if( io_transaction.iv_mode & ACCESS_MODE_READ )
{
rc = read( io_transaction.iv_address, io_transaction.iv_data );
}
else
{
rc = write( io_transaction.iv_address, io_transaction.iv_data );
}
if( rc.ok() )
{
me = ME_SUCCESS;
}
else
{
me = ME_FAILURE;
}
io_transaction.busError( me );
return rc;
}
//-----------------------------------------------------------------------------
//
fapi::ReturnCode
OciMemory::operation(Transaction& io_transaction)
{
fapi::ReturnCode rc;
ModelError me;
if( io_transaction.iv_mode & ACCESS_MODE_READ )
{
me = iv_memory->read( (uint32_t)io_transaction.iv_offset, io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES );
if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough )
{
rc = read( io_transaction.iv_address, io_transaction.iv_data );
if( rc.ok() )
{
me = ME_SUCCESS;
}
else
{
me = ME_FAILURE;
}
} else if (me) {
FAPI_ERR("Read of OCI memory at address 0x%08x failed",
io_transaction.iv_address);
iv_memory->dump();
FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_MEMORY_ACCESS_ERROR);
}
}
else
{
me = iv_memory->write( (uint32_t)io_transaction.iv_offset, io_transaction.iv_data, TRANSACTION_SIZE_IN_BYTES );
if( me == ME_NOT_MAPPED_IN_MEMORY && iv_passThrough )
{
rc = write( io_transaction.iv_address, io_transaction.iv_data );
if( rc.ok() )
{
me = ME_SUCCESS;
}
else
{
me = ME_FAILURE;
}
} else if (me) {
FAPI_ERR("Write to OCI memory at address 0x%08x failed",
io_transaction.iv_address);
iv_memory->dump();
FAPI_SET_HWP_ERROR(rc, RC_POREVE_OCI_MEMORY_ACCESS_ERROR);
}
}
io_transaction.busError( me );
return rc;
}
