void tlm_dfs::b_transport(ac_tlm2_payload &payload,
sc_core::sc_time &time_info) {
int temp;
time_info = time_info + sc_core::sc_time(TIME_DFS, SC_NS);
uint32_t addr = (uint32_t)payload.get_address();
unsigned char *d = payload.get_data_ptr();
tlm_command command = payload.get_command();
unsigned int procId = payload.get_streaming_width();
if (measures)
count_dfs++;
uint32_t *T = reinterpret_cast<uint32_t *>(d);
switch (command) {
case TLM_READ_COMMAND:
T[0] = getPowerState(procId);
if (DFS_DEBUG) {
printf("\nDFS: tlm_dfs received a READ request from processor %d",
procId);
printf("\nDFS: Current Power State -> %d", T[0]); //*d);
}
payload.set_response_status(tlm::TLM_OK_RESPONSE);
break;
case TLM_WRITE_COMMAND:
temp = (int)T[0];
#ifdef AC_GUEST_BIG_ENDIAN
temp = be32toh(temp);
#endif
if (DFS_DEBUG) {
printf("\nDFS: received a WRITE request from processor %d", procId);
printf("\nDFS: Current Power State -> %d", getPowerState(procId));
printf("\nDFS: New Required Power State -> %d", temp);
}
setPowerState(procId, temp);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
break;
default:
break;
}
if (DFS_DEBUG)
printf("\ntlm_dfs b_transport returning");
wait(TIME_DFS, SC_NS);
}
void tlm_dir::b_transport( ac_tlm2_payload &payload, sc_core::sc_time &time_info ) {
tlm_payload_dir_extension *payloadExt;
time_info = time_info + sc_core::sc_time(1,SC_NS);
int nCache=-1;
bool validation=false;
tlm::tlm_extension_base* base;
base = payload.get_extension(0);
payloadExt = reinterpret_cast<tlm_payload_dir_extension*>(base);
if(payloadExt != 0)
{
nCache = payloadExt->getnumberCache(); //id do processador
uint32_t address =-1;
address= payloadExt->getAddress(); //endereco do dado armazenado
int cacheIndex = payloadExt->getCacheIndex(); //indice do vetor da cache
int rule = payloadExt->getRule(); //comando requisitado
if(rule == 0){
int nWay = payloadExt->getNWay();
int index_size = payloadExt->getIndex_size();
dir->start(nWay, index_size);
}
if(rule == 1) //Cache leu dado da memoria, atualizar valor no diretorio
{
dir->validate(nCache, address, cacheIndex);
}
if(rule==2) //aconteceu escrita na memoria, invalidar todos os outros processadores diferentes de nCache
{
dir->unvalidate(nCache, address, cacheIndex);
}
if(rule == 3) //Verificar se dado da cache esta Valido
{
validation = dir->checkValidation(nCache, address, cacheIndex);
payloadExt->setValidation(validation);
}
}
tlm_command command = payload.get_command();
uint32_t addr = (uint32_t) payload.get_address();
unsigned char* data_pointer = payload.get_data_ptr();
unsigned int len = payload.get_data_length();
unsigned int resp;
payload.set_response_status(tlm::TLM_OK_RESPONSE);
return;
}
void tlm_memory::b_transport(ac_tlm2_payload &payload,
sc_core::sc_time &time_info) {
time_info = time_info + sc_core::sc_time(TIME_MEMORY, SC_NS);
uint32_t addr = (uint32_t)payload.get_address();
unsigned char *data_pointer = payload.get_data_ptr();
unsigned int len = payload.get_data_length();
/* Novo atributo recuperado - numero do processador */
unsigned int procId = payload.get_streaming_width();
tlm_command command = payload.get_command();
if (MEMORY_DEBUG)
printf("\nMEMORY TRANSPORT: command--> %d address--> %d lenght-->%u",
command, addr, len);
// if (addr > MEM_SIZE) printf("\nMEMORY TRANSPORT WARNING: address %d out of
// limits...MEM_SIZE=%d", addr,MEM_SIZE);
switch (command) {
case TLM_READ_COMMAND:
count_read_memory++;
readm(addr, data_pointer, len);
/* Incremento de leitura do vetor processors, de acordo com o processador
* que leu dado */
if (procId > this->processorsReads.size()) {
this->processorsReads.resize(procId);
}
this->processorsReads[procId] = this->processorsReads[procId] + 1;
payload.set_response_status(tlm::TLM_OK_RESPONSE);
break;
case TLM_WRITE_COMMAND:
count_write_memory++;
writem(addr, data_pointer, len);
if (procId > this->processorsWrites.size()) {
this->processorsWrites.resize(procId);
}
/* Incremento de leitura do vetor processors, de acordo com o processador
* que escreveu dado */
this->processorsWrites[procId] = this->processorsWrites[procId] + 1;
payload.set_response_status(tlm::TLM_OK_RESPONSE);
break;
default:
break;
}
if (MEMORY_DEBUG)
printf("\ntlm_memory b_transport returning...");
}
void ac_noc::b_transport(ac_tlm2_payload &payload,
sc_core::sc_time &time_info) {
FLITTYPE nocaddr, memaddr;
uint32_t addr_m = (uint32_t)payload.get_address();
addressMap addr = decodeAddress(addr_m);
nocaddr = addr.nocAddress;
memaddr = addr_m - addr.startaddress;
unsigned char *data_pointer = payload.get_data_ptr();
unsigned int len = payload.get_data_length();
tlm_command command = payload.get_command();
// cout << "comando: " << command << "len: " << len << endl;
payload.set_response_status(tlm::TLM_OK_RESPONSE);
uint8_t data8;
uint16_t data16;
uint32_t data32;
switch (command) {
case TLM_READ_COMMAND: // Packet is a READ one
sendReadPacket(nocaddr, memaddr);
// response.data = receiveReadPacket();
*((uint32_t *)data_pointer) = (uint32_t)receiveReadPacket();
break;
case TLM_WRITE_COMMAND: // Packet is a WRITE
sendWritePacket(nocaddr, memaddr, (*(uint32_t *)data_pointer));
break;
default:
printf("AC_NOC TRANSPORT --> COMMAND %d IS NOT IMPLEMENTED", command);
break;
}
}