/** * Alpha test support for when we compile it into the shader instead * of using the normal fixed-function alpha test. */ void fs_visitor::emit_alpha_test() { assert(stage == MESA_SHADER_FRAGMENT); brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; const fs_builder abld = bld.annotate("Alpha test"); fs_inst *cmp; if (key->alpha_test_func == GL_ALWAYS) return; if (key->alpha_test_func == GL_NEVER) { /* f0.1 = 0 */ fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); cmp = abld.CMP(bld.null_reg_f(), some_reg, some_reg, BRW_CONDITIONAL_NEQ); } else { /* RT0 alpha */ fs_reg color = offset(outputs[0], bld, 3); /* f0.1 &= func(color, ref) */ cmp = abld.CMP(bld.null_reg_f(), color, fs_reg(key->alpha_test_ref), cond_for_alpha_func(key->alpha_test_func)); } cmp->predicate = BRW_PREDICATE_NORMAL; cmp->flag_subreg = 1; }
void fs_visitor::emit_barrier() { assert(devinfo->gen >= 7); const uint32_t barrier_id_mask = devinfo->gen >= 9 ? 0x8f000000u : 0x0f000000u; /* We are getting the barrier ID from the compute shader header */ assert(stage == MESA_SHADER_COMPUTE); fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); const fs_builder pbld = bld.exec_all().group(8, 0); /* Clear the message payload */ pbld.MOV(payload, brw_imm_ud(0u)); /* Copy the barrier id from r0.2 to the message payload reg.2 */ fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)); pbld.AND(component(payload, 2), r0_2, brw_imm_ud(barrier_id_mask)); /* Emit a gateway "barrier" message using the payload we set up, followed * by a wait instruction. */ bld.exec_all().emit(SHADER_OPCODE_BARRIER, reg_undef, payload); }
/** * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances. * * This does nothing if the shader uses gl_ClipDistance or user clipping is * disabled altogether. */ void fs_visitor::compute_clip_distance(gl_clip_plane *clip_planes) { struct brw_vue_prog_data *vue_prog_data = (struct brw_vue_prog_data *) prog_data; const struct brw_vs_prog_key *key = (const struct brw_vs_prog_key *) this->key; /* Bail unless some sort of legacy clipping is enabled */ if (key->nr_userclip_plane_consts == 0) return; /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables): * * "If a linked set of shaders forming the vertex stage contains no * static write to gl_ClipVertex or gl_ClipDistance, but the * application has requested clipping against user clip planes through * the API, then the coordinate written to gl_Position is used for * comparison against the user clip planes." * * This function is only called if the shader didn't write to * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping * if the user wrote to it; otherwise we use gl_Position. */ gl_varying_slot clip_vertex = VARYING_SLOT_CLIP_VERTEX; if (!(vue_prog_data->vue_map.slots_valid & VARYING_BIT_CLIP_VERTEX)) clip_vertex = VARYING_SLOT_POS; /* If the clip vertex isn't written, skip this. Typically this means * the GS will set up clipping. */ if (outputs[clip_vertex].file == BAD_FILE) return; setup_uniform_clipplane_values(clip_planes); const fs_builder abld = bld.annotate("user clip distances"); this->outputs[VARYING_SLOT_CLIP_DIST0] = vgrf(glsl_type::vec4_type); this->output_components[VARYING_SLOT_CLIP_DIST0] = 4; this->outputs[VARYING_SLOT_CLIP_DIST1] = vgrf(glsl_type::vec4_type); this->output_components[VARYING_SLOT_CLIP_DIST1] = 4; for (int i = 0; i < key->nr_userclip_plane_consts; i++) { fs_reg u = userplane[i]; fs_reg output = outputs[VARYING_SLOT_CLIP_DIST0 + i / 4]; output.reg_offset = i & 3; abld.MUL(output, outputs[clip_vertex], u); for (int j = 1; j < 4; j++) { u.nr = userplane[i].nr + j; abld.MAD(output, output, offset(outputs[clip_vertex], bld, j), u); } } }
/** * Emit an untyped surface atomic opcode. \p dims determines the number * of components of the address and \p rsize the number of components of * the returned value (either zero or one). */ fs_reg emit_untyped_atomic(const fs_builder &bld, const fs_reg &surface, const fs_reg &addr, const fs_reg &src0, const fs_reg &src1, unsigned dims, unsigned rsize, unsigned op, brw_predicate pred) { /* FINISHME: Factor out this frequently recurring pattern into a * helper function. */ const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE); const fs_reg srcs[] = { src0, src1 }; const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, n); bld.LOAD_PAYLOAD(tmp, srcs, n, 0); return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, addr, tmp, surface, dims, op, rsize, pred); }
void fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count) { int slot, urb_offset, length; int starting_urb_offset = 0; const struct brw_vue_prog_data *vue_prog_data = (const struct brw_vue_prog_data *) this->prog_data; const struct brw_vs_prog_key *vs_key = (const struct brw_vs_prog_key *) this->key; const GLbitfield64 psiz_mask = VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PSIZ; const struct brw_vue_map *vue_map = &vue_prog_data->vue_map; bool flush; fs_reg sources[8]; /* If we don't have any valid slots to write, just do a minimal urb write * send to terminate the shader. This includes 1 slot of undefined data, * because it's invalid to write 0 data: * * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions - * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read > * Write Data Payload: * * "The write data payload can be between 1 and 8 message phases long." */ if (vue_map->slots_valid == 0) { fs_reg payload = fs_reg(VGRF, alloc.allocate(2), BRW_REGISTER_TYPE_UD); bld.exec_all().MOV(payload, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD))); fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload); inst->eot = true; inst->mlen = 2; inst->offset = 1; return; } opcode opcode = SHADER_OPCODE_URB_WRITE_SIMD8; int header_size = 1; fs_reg per_slot_offsets; if (stage == MESA_SHADER_GEOMETRY) { const struct brw_gs_prog_data *gs_prog_data = (const struct brw_gs_prog_data *) this->prog_data; /* We need to increment the Global Offset to skip over the control data * header and the extra "Vertex Count" field (1 HWord) at the beginning * of the VUE. We're counting in OWords, so the units are doubled. */ starting_urb_offset = 2 * gs_prog_data->control_data_header_size_hwords; if (gs_prog_data->static_vertex_count == -1) starting_urb_offset += 2; /* We also need to use per-slot offsets. The per-slot offset is the * Vertex Count. SIMD8 mode processes 8 different primitives at a * time; each may output a different number of vertices. */ opcode = SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT; header_size++; /* The URB offset is in 128-bit units, so we need to multiply by 2 */ const int output_vertex_size_owords = gs_prog_data->output_vertex_size_hwords * 2; fs_reg offset; if (gs_vertex_count.file == IMM) { per_slot_offsets = fs_reg(output_vertex_size_owords * gs_vertex_count.ud); } else { per_slot_offsets = vgrf(glsl_type::int_type); bld.MUL(per_slot_offsets, gs_vertex_count, fs_reg(output_vertex_size_owords)); } } length = 0; urb_offset = starting_urb_offset; flush = false; for (slot = 0; slot < vue_map->num_slots; slot++) { int varying = vue_map->slot_to_varying[slot]; switch (varying) { case VARYING_SLOT_PSIZ: { /* The point size varying slot is the vue header and is always in the * vue map. But often none of the special varyings that live there * are written and in that case we can skip writing to the vue * header, provided the corresponding state properly clamps the * values further down the pipeline. */ if ((vue_map->slots_valid & psiz_mask) == 0) { assert(length == 0); urb_offset++; break; } fs_reg zero(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD); bld.MOV(zero, fs_reg(0u)); sources[length++] = zero; if (vue_map->slots_valid & VARYING_BIT_LAYER) sources[length++] = this->outputs[VARYING_SLOT_LAYER]; else sources[length++] = zero; if (vue_map->slots_valid & VARYING_BIT_VIEWPORT) sources[length++] = this->outputs[VARYING_SLOT_VIEWPORT]; else sources[length++] = zero; if (vue_map->slots_valid & VARYING_BIT_PSIZ) sources[length++] = this->outputs[VARYING_SLOT_PSIZ]; else sources[length++] = zero; break; } case BRW_VARYING_SLOT_NDC: case VARYING_SLOT_EDGE: unreachable("unexpected scalar vs output"); break; default: /* gl_Position is always in the vue map, but isn't always written by * the shader. Other varyings (clip distances) get added to the vue * map but don't always get written. In those cases, the * corresponding this->output[] slot will be invalid we and can skip * the urb write for the varying. If we've already queued up a vue * slot for writing we flush a mlen 5 urb write, otherwise we just * advance the urb_offset. */ if (varying == BRW_VARYING_SLOT_PAD || this->outputs[varying].file == BAD_FILE) { if (length > 0) flush = true; else urb_offset++; break; } if (stage == MESA_SHADER_VERTEX && vs_key->clamp_vertex_color && (varying == VARYING_SLOT_COL0 || varying == VARYING_SLOT_COL1 || varying == VARYING_SLOT_BFC0 || varying == VARYING_SLOT_BFC1)) { /* We need to clamp these guys, so do a saturating MOV into a * temp register and use that for the payload. */ for (int i = 0; i < 4; i++) { fs_reg reg = fs_reg(VGRF, alloc.allocate(1), outputs[varying].type); fs_reg src = offset(this->outputs[varying], bld, i); set_saturate(true, bld.MOV(reg, src)); sources[length++] = reg; } } else { for (unsigned i = 0; i < output_components[varying]; i++) sources[length++] = offset(this->outputs[varying], bld, i); for (unsigned i = output_components[varying]; i < 4; i++) sources[length++] = fs_reg(0); } break; } const fs_builder abld = bld.annotate("URB write"); /* If we've queued up 8 registers of payload (2 VUE slots), if this is * the last slot or if we need to flush (see BAD_FILE varying case * above), emit a URB write send now to flush out the data. */ int last = slot == vue_map->num_slots - 1; if (length == 8 || last) flush = true; if (flush) { fs_reg *payload_sources = ralloc_array(mem_ctx, fs_reg, length + header_size); fs_reg payload = fs_reg(VGRF, alloc.allocate(length + header_size), BRW_REGISTER_TYPE_F); payload_sources[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD)); if (opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT) payload_sources[1] = per_slot_offsets; memcpy(&payload_sources[header_size], sources, length * sizeof sources[0]); abld.LOAD_PAYLOAD(payload, payload_sources, length + header_size, header_size); fs_inst *inst = abld.emit(opcode, reg_undef, payload); inst->eot = last && stage == MESA_SHADER_VERTEX; inst->mlen = length + header_size; inst->offset = urb_offset; urb_offset = starting_urb_offset + slot + 1; length = 0; flush = false; } } }
/** Emits the interpolation for the varying inputs. */ void fs_visitor::emit_interpolation_setup_gen6() { struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); fs_builder abld = bld.annotate("compute pixel centers"); if (devinfo->gen >= 8 || dispatch_width == 8) { /* The "Register Region Restrictions" page says for BDW (and newer, * presumably): * * "When destination spans two registers, the source may be one or * two registers. The destination elements must be evenly split * between the two registers." * * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to * compute our pixel centers. */ fs_reg int_pixel_xy(VGRF, alloc.allocate(dispatch_width / 8), BRW_REGISTER_TYPE_UW); const fs_builder dbld = abld.exec_all().group(dispatch_width * 2, 0); dbld.ADD(int_pixel_xy, fs_reg(stride(suboffset(g1_uw, 4), 1, 4, 0)), fs_reg(brw_imm_v(0x11001010))); this->pixel_x = vgrf(glsl_type::float_type); this->pixel_y = vgrf(glsl_type::float_type); abld.emit(FS_OPCODE_PIXEL_X, this->pixel_x, int_pixel_xy); abld.emit(FS_OPCODE_PIXEL_Y, this->pixel_y, int_pixel_xy); } else { /* The "Register Region Restrictions" page says for SNB, IVB, HSW: * * "When destination spans two registers, the source MUST span two * registers." * * Since the GRF source of the ADD will only read a single register, we * must do two separate ADDs in SIMD16. */ fs_reg int_pixel_x = vgrf(glsl_type::uint_type); fs_reg int_pixel_y = vgrf(glsl_type::uint_type); int_pixel_x.type = BRW_REGISTER_TYPE_UW; int_pixel_y.type = BRW_REGISTER_TYPE_UW; abld.ADD(int_pixel_x, fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), fs_reg(brw_imm_v(0x10101010))); abld.ADD(int_pixel_y, fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), fs_reg(brw_imm_v(0x11001100))); /* As of gen6, we can no longer mix float and int sources. We have * to turn the integer pixel centers into floats for their actual * use. */ this->pixel_x = vgrf(glsl_type::float_type); this->pixel_y = vgrf(glsl_type::float_type); abld.MOV(this->pixel_x, int_pixel_x); abld.MOV(this->pixel_y, int_pixel_y); } abld = bld.annotate("compute pos.w"); this->pixel_w = fs_reg(brw_vec8_grf(payload.source_w_reg, 0)); this->wpos_w = vgrf(glsl_type::float_type); abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) { uint8_t reg = payload.barycentric_coord_reg[i]; this->delta_xy[i] = fs_reg(brw_vec16_grf(reg, 0)); } }
/** Emits the interpolation for the varying inputs. */ void fs_visitor::emit_interpolation_setup_gen6() { struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); fs_builder abld = bld.annotate("compute pixel centers"); if (devinfo->gen >= 8 || dispatch_width == 8) { /* The "Register Region Restrictions" page says for BDW (and newer, * presumably): * * "When destination spans two registers, the source may be one or * two registers. The destination elements must be evenly split * between the two registers." * * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to * compute our pixel centers. */ fs_reg int_pixel_xy(VGRF, alloc.allocate(dispatch_width / 8), BRW_REGISTER_TYPE_UW); const fs_builder dbld = abld.exec_all().group(dispatch_width * 2, 0); dbld.ADD(int_pixel_xy, fs_reg(stride(suboffset(g1_uw, 4), 1, 4, 0)), fs_reg(brw_imm_v(0x11001010))); this->pixel_x = vgrf(glsl_type::float_type); this->pixel_y = vgrf(glsl_type::float_type); abld.emit(FS_OPCODE_PIXEL_X, this->pixel_x, int_pixel_xy); abld.emit(FS_OPCODE_PIXEL_Y, this->pixel_y, int_pixel_xy); } else { /* The "Register Region Restrictions" page says for SNB, IVB, HSW: * * "When destination spans two registers, the source MUST span two * registers." * * Since the GRF source of the ADD will only read a single register, we * must do two separate ADDs in SIMD16. */ fs_reg int_pixel_x = vgrf(glsl_type::uint_type); fs_reg int_pixel_y = vgrf(glsl_type::uint_type); int_pixel_x.type = BRW_REGISTER_TYPE_UW; int_pixel_y.type = BRW_REGISTER_TYPE_UW; abld.ADD(int_pixel_x, fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), fs_reg(brw_imm_v(0x10101010))); abld.ADD(int_pixel_y, fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), fs_reg(brw_imm_v(0x11001100))); /* As of gen6, we can no longer mix float and int sources. We have * to turn the integer pixel centers into floats for their actual * use. */ this->pixel_x = vgrf(glsl_type::float_type); this->pixel_y = vgrf(glsl_type::float_type); abld.MOV(this->pixel_x, int_pixel_x); abld.MOV(this->pixel_y, int_pixel_y); } abld = bld.annotate("compute pos.w"); this->pixel_w = fs_reg(brw_vec8_grf(payload.source_w_reg, 0)); this->wpos_w = vgrf(glsl_type::float_type); abld.emit(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w); struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(prog_data); uint32_t centroid_modes = wm_prog_data->barycentric_interp_modes & (1 << BRW_BARYCENTRIC_PERSPECTIVE_CENTROID | 1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID); for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) { uint8_t reg = payload.barycentric_coord_reg[i]; this->delta_xy[i] = fs_reg(brw_vec16_grf(reg, 0)); if (devinfo->needs_unlit_centroid_workaround && (centroid_modes & (1 << i))) { /* Get the pixel/sample mask into f0 so that we know which * pixels are lit. Then, for each channel that is unlit, * replace the centroid data with non-centroid data. */ bld.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS); uint8_t pixel_reg = payload.barycentric_coord_reg[i - 1]; set_predicate_inv(BRW_PREDICATE_NORMAL, true, bld.half(0).MOV(brw_vec8_grf(reg, 0), brw_vec8_grf(pixel_reg, 0))); set_predicate_inv(BRW_PREDICATE_NORMAL, true, bld.half(0).MOV(brw_vec8_grf(reg + 1, 0), brw_vec8_grf(pixel_reg + 1, 0))); if (dispatch_width == 16) { set_predicate_inv(BRW_PREDICATE_NORMAL, true, bld.half(1).MOV(brw_vec8_grf(reg + 2, 0), brw_vec8_grf(pixel_reg + 2, 0))); set_predicate_inv(BRW_PREDICATE_NORMAL, true, bld.half(1).MOV(brw_vec8_grf(reg + 3, 0), brw_vec8_grf(pixel_reg + 3, 0))); } assert(dispatch_width != 32); /* not implemented yet */ } } }