unsigned AArch64InstrInfo::estimateRSStackLimit(MachineFunction &MF) const {
unsigned Limit = (1 << 16) - 1;
for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
I != E; ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
if (!I->getOperand(i).isFI()) continue;
// When using ADDxxi_lsl0_s to get the address of a stack object, 0xfff
// is the largest offset guaranteed to fit in the immediate offset.
if (I->getOpcode() == AArch64::ADDxxi_lsl0_s) {
Limit = std::min(Limit, 0xfffu);
break;
}
int AccessScale, MinOffset, MaxOffset;
getAddressConstraints(*I, AccessScale, MinOffset, MaxOffset);
Limit = std::min(Limit, static_cast<unsigned>(MaxOffset));
break; // At most one FI per instruction
}
}
}
return Limit;
}
/// \brief Replace loop instructions with the constant extended version.
void HexagonFixupHwLoops::useExtLoopInstr(MachineFunction &MF,
MachineBasicBlock::iterator &MII) {
const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
MachineBasicBlock *MBB = MII->getParent();
DebugLoc DL = MII->getDebugLoc();
MachineInstrBuilder MIB;
unsigned newOp;
switch (MII->getOpcode()) {
case Hexagon::J2_loop0r:
newOp = Hexagon::J2_loop0rext;
break;
case Hexagon::J2_loop0i:
newOp = Hexagon::J2_loop0iext;
break;
case Hexagon::J2_loop1r:
newOp = Hexagon::J2_loop1rext;
break;
case Hexagon::J2_loop1i:
newOp = Hexagon::J2_loop1iext;
break;
default:
llvm_unreachable("Invalid Hardware Loop Instruction.");
}
MIB = BuildMI(*MBB, MII, DL, TII->get(newOp));
for (unsigned i = 0; i < MII->getNumOperands(); ++i)
MIB.add(MII->getOperand(i));
}
static bool hasImmInstruction(MachineBasicBlock::iterator &candidate) {
// Any instruction with an immediate mode operand greater than
// 16-bits requires an implicit IMM instruction.
unsigned numOper = candidate->getNumOperands();
for (unsigned op = 0; op < numOper; ++op) {
MachineOperand &mop = candidate->getOperand(op);
// The operand requires more than 16-bits to represent.
if (mop.isImm() && (mop.getImm() < -0x8000 || mop.getImm() > 0x7fff))
return true;
// We must assume that unknown immediate values require more than
// 16-bits to represent.
if (mop.isGlobal() || mop.isSymbol())
return true;
// FIXME: we could probably check to see if the FP value happens
// to not need an IMM instruction. For now we just always
// assume that FP values do.
if (mop.isFPImm())
return true;
}
return false;
}
bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
MachineBasicBlock &MBB,
LiveVariables &LV,
MachineLoopInfo *MLI) {
if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
return false; // Quick exit for basic blocks without PHIs.
bool Changed = false;
for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
BBI != BBE && BBI->isPHI(); ++BBI) {
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
unsigned Reg = BBI->getOperand(i).getReg();
MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
// We break edges when registers are live out from the predecessor block
// (not considering PHI nodes). If the register is live in to this block
// anyway, we would gain nothing from splitting.
// Avoid splitting backedges of loops. It would introduce small
// out-of-line blocks into the loop which is very bad for code placement.
if (PreMBB != &MBB &&
!LV.isLiveIn(Reg, MBB) && LV.isLiveOut(Reg, *PreMBB)) {
if (!MLI ||
!(MLI->getLoopFor(PreMBB) == MLI->getLoopFor(&MBB) &&
MLI->isLoopHeader(&MBB))) {
if (PreMBB->SplitCriticalEdge(&MBB, this)) {
Changed = true;
++NumCriticalEdgesSplit;
}
}
}
}
}
return Changed;
}
void GCMachineCodeAnalysis::FindRegisterRoots(MachineFunction &MF) {
const TargetFrameLowering *TFI = TM->getFrameLowering();
assert(TFI && "TargetRegisterInfo not available!");
unsigned PointIndex = 0;
for (MachineFunction::iterator BBI = MF.begin(),
BBE = MF.end(); BBI != BBE; ++BBI) {
for (MachineBasicBlock::iterator MI = BBI->begin(),
ME = BBI->end(); MI != ME; ++MI) {
if (MI->isGCLabel())
PointIndex = FI->getPointIndex(MI->getOperand(0).getMCSymbol());
if (!MI->isGCRegRoot())
continue;
unsigned RootIndex = MI->getOperand(MI->getNumOperands() - 1).getImm();
if (FI->isRootGlobal(RootIndex))
continue;
FI->setLive(PointIndex, RootIndex, true);
if (!FI->getRoot(RootIndex).isReg())
continue;
GCRootLoc Loc;
Loc.PhysReg = MI->getOperand(0).getReg();
FI->setRootLoc(RootIndex, Loc);
}
}
}
void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI,
SmallSet<unsigned, 32>& RegDefs,
SmallSet<unsigned, 32>& RegUses)
{
// Call defines o7, which is visible to the instruction in delay slot.
RegDefs.insert(SP::O7);
switch(MI->getOpcode()) {
default: llvm_unreachable("Unknown opcode.");
case SP::CALL: break;
case SP::CALLrr:
case SP::CALLri:
assert(MI->getNumOperands() >= 2);
const MachineOperand &Reg = MI->getOperand(0);
assert(Reg.isReg() && "CALL first operand is not a register.");
assert(Reg.isUse() && "CALL first operand is not a use.");
RegUses.insert(Reg.getReg());
const MachineOperand &Operand1 = MI->getOperand(1);
if (Operand1.isImm() || Operand1.isGlobal())
break;
assert(Operand1.isReg() && "CALLrr second operand is not a register.");
assert(Operand1.isUse() && "CALLrr second operand is not a use.");
RegUses.insert(Operand1.getReg());
break;
}
}
static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ++I) {
MachineBasicBlock *MBB = I;
SmallSetVector<MachineBasicBlock*, 8> Preds(MBB->pred_begin(),
MBB->pred_end());
MachineBasicBlock::iterator MI = MBB->begin();
while (MI != MBB->end()) {
if (!MI->isPHI())
break;
for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(),
PE = Preds.end(); PI != PE; ++PI) {
MachineBasicBlock *PredBB = *PI;
bool Found = false;
for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB();
if (PHIBB == PredBB) {
Found = true;
break;
}
}
if (!Found) {
dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
dbgs() << " missing input from predecessor BB#"
<< PredBB->getNumber() << '\n';
llvm_unreachable(0);
}
}
for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB();
if (CheckExtra && !Preds.count(PHIBB)) {
dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber()
<< ": " << *MI;
dbgs() << " extra input from predecessor BB#"
<< PHIBB->getNumber() << '\n';
llvm_unreachable(0);
}
if (PHIBB->getNumber() < 0) {
dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
dbgs() << " non-existing BB#" << PHIBB->getNumber() << '\n';
llvm_unreachable(0);
}
}
++MI;
}
}
}
// We have identified this II could be feeder to NVJ,
// verify that it can be.
static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
const TargetRegisterInfo *TRI,
MachineBasicBlock::iterator II,
MachineBasicBlock::iterator end,
MachineBasicBlock::iterator skip,
MachineFunction &MF) {
// Predicated instruction can not be feeder to NVJ.
if (QII->isPredicated(*II))
return false;
// Bail out if feederReg is a paired register (double regs in
// our case). One would think that we can check to see if a given
// register cmpReg1 or cmpReg2 is a sub register of feederReg
// using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
// before the callsite of this function
// But we can not as it comes in the following fashion.
// %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
// %R0<def> = KILL %R0, %D0<imp-use,kill>
// %P0<def> = CMPEQri %R0<kill>, 0
// Hence, we need to check if it's a KILL instruction.
if (II->getOpcode() == TargetOpcode::KILL)
return false;
// Make sure there there is no 'def' or 'use' of any of the uses of
// feeder insn between it's definition, this MI and jump, jmpInst
// skipping compare, cmpInst.
// Here's the example.
// r21=memub(r22+r24<<#0)
// p0 = cmp.eq(r21, #0)
// r4=memub(r3+r21<<#0)
// if (p0.new) jump:t .LBB29_45
// Without this check, it will be converted into
// r4=memub(r3+r21<<#0)
// r21=memub(r22+r24<<#0)
// p0 = cmp.eq(r21, #0)
// if (p0.new) jump:t .LBB29_45
// and result WAR hazards if converted to New Value Jump.
for (unsigned i = 0; i < II->getNumOperands(); ++i) {
if (II->getOperand(i).isReg() &&
(II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
MachineBasicBlock::iterator localII = II;
++localII;
unsigned Reg = II->getOperand(i).getReg();
for (MachineBasicBlock::iterator localBegin = localII;
localBegin != end; ++localBegin) {
if (localBegin == skip ) continue;
// Check for Subregisters too.
if (localBegin->modifiesRegister(Reg, TRI) ||
localBegin->readsRegister(Reg, TRI))
return false;
}
}
}
return true;
}
/// saveScavengerRegister - Spill the register so it can be used by the
/// register scavenger. Return true.
bool ThumbRegisterInfo::saveScavengerRegister(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC,
unsigned Reg) const {
const ARMSubtarget &STI = MBB.getParent()->getSubtarget<ARMSubtarget>();
if (!STI.isThumb1Only())
return ARMBaseRegisterInfo::saveScavengerRegister(MBB, I, UseMI, RC, Reg);
// Thumb1 can't use the emergency spill slot on the stack because
// ldr/str immediate offsets must be positive, and if we're referencing
// off the frame pointer (if, for example, there are alloca() calls in
// the function, the offset will be negative. Use R12 instead since that's
// a call clobbered register that we know won't be used in Thumb1 mode.
const TargetInstrInfo &TII = *STI.getInstrInfo();
DebugLoc DL;
BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
.addReg(ARM::R12, RegState::Define)
.addReg(Reg, RegState::Kill)
.add(predOps(ARMCC::AL));
// The UseMI is where we would like to restore the register. If there's
// interference with R12 before then, however, we'll need to restore it
// before that instead and adjust the UseMI.
bool done = false;
for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
if (II->isDebugInstr())
continue;
// If this instruction affects R12, adjust our restore point.
for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = II->getOperand(i);
if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
UseMI = II;
done = true;
break;
}
if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
continue;
if (MO.getReg() == ARM::R12) {
UseMI = II;
done = true;
break;
}
}
}
// Restore the register from R12
BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr))
.addReg(Reg, RegState::Define)
.addReg(ARM::R12, RegState::Kill)
.add(predOps(ARMCC::AL));
return true;
}
/// InsertCopies - insert copies into MBB and all of its successors
void StrongPHIElimination::InsertCopies(MachineDomTreeNode* MDTN,
SmallPtrSet<MachineBasicBlock*, 16>& visited) {
MachineBasicBlock* MBB = MDTN->getBlock();
visited.insert(MBB);
std::set<unsigned> pushed;
LiveIntervals& LI = getAnalysis<LiveIntervals>();
// Rewrite register uses from Stacks
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
if (I->isPHI())
continue;
for (unsigned i = 0; i < I->getNumOperands(); ++i)
if (I->getOperand(i).isReg() &&
Stacks[I->getOperand(i).getReg()].size()) {
// Remove the live range for the old vreg.
LiveInterval& OldInt = LI.getInterval(I->getOperand(i).getReg());
LiveInterval::iterator OldLR =
OldInt.FindLiveRangeContaining(LI.getInstructionIndex(I).getUseIndex());
if (OldLR != OldInt.end())
OldInt.removeRange(*OldLR, true);
// Change the register
I->getOperand(i).setReg(Stacks[I->getOperand(i).getReg()].back());
// Add a live range for the new vreg
LiveInterval& Int = LI.getInterval(I->getOperand(i).getReg());
VNInfo* FirstVN = *Int.vni_begin();
FirstVN->setHasPHIKill(false);
LiveRange LR (LI.getMBBStartIdx(I->getParent()),
LI.getInstructionIndex(I).getUseIndex().getNextSlot(),
FirstVN);
Int.addRange(LR);
}
}
// Schedule the copies for this block
ScheduleCopies(MBB, pushed);
// Recur down the dominator tree.
for (MachineDomTreeNode::iterator I = MDTN->begin(),
E = MDTN->end(); I != E; ++I)
if (!visited.count((*I)->getBlock()))
InsertCopies(*I, visited);
// As we exit this block, pop the names we pushed while processing it
for (std::set<unsigned>::iterator I = pushed.begin(),
E = pushed.end(); I != E; ++I)
Stacks[*I].pop_back();
}
bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
bool &sawLoad,
bool &sawStore,
SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses)
{
if (candidate->isImplicitDef() || candidate->isKill())
return true;
if (candidate->mayLoad()) {
sawLoad = true;
if (sawStore)
return true;
}
if (candidate->mayStore()) {
if (sawStore)
return true;
sawStore = true;
if (sawLoad)
return true;
}
for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
const MachineOperand &MO = candidate->getOperand(i);
if (!MO.isReg())
continue; // skip
unsigned Reg = MO.getReg();
if (MO.isDef()) {
// check whether Reg is defined or used before delay slot.
if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
return true;
}
if (MO.isUse()) {
// check whether Reg is defined before delay slot.
if (IsRegInSet(RegDefs, Reg))
return true;
}
}
unsigned Opcode = candidate->getOpcode();
// LD and LDD may have NOPs inserted afterwards in the case of some LEON
// processors, so we can't use the delay slot if this feature is switched-on.
if (Subtarget->insertNOPLoad()
&&
Opcode >= SP::LDDArr && Opcode <= SP::LDrr)
return true;
return false;
}
static unsigned getLastRealOperand(MachineBasicBlock::iterator &instr) {
switch (instr->getOpcode()) {
default: return instr->getNumOperands();
// These instructions have a variable number of operands but the first two
// are the "real" operands that we care about during hazard detection.
case MBlaze::BRLID:
case MBlaze::BRALID:
case MBlaze::BRLD:
case MBlaze::BRALD:
return 2;
}
}
/// calculateCallsInformation - Calculate the MaxCallFrameSize and AdjustsStack
/// variables for the function's frame information and eliminate call frame
/// pseudo instructions.
void PEI::calculateCallsInformation(MachineFunction &Fn) {
const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
MachineFrameInfo *MFI = Fn.getFrameInfo();
unsigned MaxCallFrameSize = 0;
bool AdjustsStack = MFI->adjustsStack();
// Get the function call frame set-up and tear-down instruction opcode
int FrameSetupOpcode = TII.getCallFrameSetupOpcode();
int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
// Early exit for targets which have no call frame setup/destroy pseudo
// instructions.
if (FrameSetupOpcode == -1 && FrameDestroyOpcode == -1)
return;
std::vector<MachineBasicBlock::iterator> FrameSDOps;
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I)
if (I->getOpcode() == FrameSetupOpcode ||
I->getOpcode() == FrameDestroyOpcode) {
assert(I->getNumOperands() >= 1 && "Call Frame Setup/Destroy Pseudo"
" instructions should have a single immediate argument!");
unsigned Size = I->getOperand(0).getImm();
if (Size > MaxCallFrameSize) MaxCallFrameSize = Size;
AdjustsStack = true;
FrameSDOps.push_back(I);
} else if (I->isInlineAsm()) {
// Some inline asm's need a stack frame, as indicated by operand 1.
unsigned ExtraInfo = I->getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
AdjustsStack = true;
}
MFI->setAdjustsStack(AdjustsStack);
MFI->setMaxCallFrameSize(MaxCallFrameSize);
for (std::vector<MachineBasicBlock::iterator>::iterator
i = FrameSDOps.begin(), e = FrameSDOps.end(); i != e; ++i) {
MachineBasicBlock::iterator I = *i;
// If call frames are not being included as part of the stack frame, and
// the target doesn't indicate otherwise, remove the call frame pseudos
// here. The sub/add sp instruction pairs are still inserted, but we don't
// need to track the SP adjustment for frame index elimination.
if (TFI->canSimplifyCallFramePseudos(Fn))
RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
}
}
void DSPSEInstrInfo::ExpandMovGR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned Opc1,unsigned Opc2) const {
unsigned SrcReg = 0;
unsigned DesReg = 0;
unsigned num = I->getNumOperands();
MachineFunction &MF = *MBB.getParent();
DesReg = I->getOperand(0).getReg();
SrcReg = I->getOperand(1).getReg();
unsigned MOTy = I->getOperand(2).getType();
int imm = 0;
std::cout << "num is " << num << std::endl;
std::cout << "type0 is " << I->getOperand(0).getType() << std::endl;
std::cout << "type1 is " << I->getOperand(1).getType() << std::endl;
std::cout << "type2 is " << I->getOperand(2).getType() << std::endl;
switch (MOTy)
{
default:
llvm_unreachable("wrong type");
break;
case MachineOperand::MO_ConstantPoolIndex: {
std::cout << "constant pool" << std::endl;
BuildMI(MBB, I, I->getDebugLoc(), get(Opc2), DesReg).addOperand(I->getOperand(1)).addOperand(I->getOperand(2));
std::cout << "Lo is" << imm << std::endl;
BuildMI(MBB, I, I->getDebugLoc(), get(Opc1), DesReg).addOperand(I->getOperand(1)).addOperand(I->getOperand(2));
std::cout << "Hi is" << imm << std::endl;
}
break;
case MachineOperand::MO_Immediate: {
std::cout << "immediate" << std::endl;
imm = I->getOperand(2).getImm();
std::cout << "imm is" << imm << std::endl;
std::cout << "desreg is" << DesReg << std::endl;
std::cout << "Srcreg is" << DesReg << std::endl;
short Lo = imm;
short Hi = (imm) >> 16;
BuildMI(MBB, I, I->getDebugLoc(), get(Opc2), DesReg).addReg(SrcReg).addImm(Lo);
std::cout << "Lo is" << Lo << std::endl;
BuildMI(MBB, I, I->getDebugLoc(), get(Opc1), DesReg).addReg(SrcReg).addImm(Hi);
std::cout << "Hi is" << Hi << std::endl;
}
break;
}
}
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
MachineBasicBlock::iterator I,
int SPAdj) {
assert(ScavengingFrameIndex >= 0 &&
"Cannot scavenge a register without an emergency spill slot!");
// Mask off the registers which are not in the TargetRegisterClass.
BitVector Candidates(NumPhysRegs, false);
CreateRegClassMask(RC, Candidates);
// Do not include reserved registers.
Candidates ^= ReservedRegs & Candidates;
// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
if (MO.isReg())
Candidates.reset(MO.getReg());
}
// Find the register whose use is furthest away.
MachineBasicBlock::iterator UseMI;
unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
// If we found an unused register there is no reason to spill it. We have
// probably found a callee-saved register that has been saved in the
// prologue, but happens to be unused at this point.
if (!isAliasUsed(SReg))
return SReg;
assert(ScavengedReg == 0 &&
"Scavenger slot is live, unable to scavenge another register!");
// Avoid infinite regress
ScavengedReg = SReg;
// Spill the scavenged register before I.
TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
MachineBasicBlock::iterator II = prior(I);
TRI->eliminateFrameIndex(II, SPAdj, this);
// Restore the scavenged register before its use (or first terminator).
TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC);
ScavengeRestore = prior(UseMI);
// Doing this here leads to infinite regress.
// ScavengedReg = SReg;
ScavengedRC = RC;
return SReg;
}
MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A,
MachineBasicBlock *B) {
assert(A && B && "Missing MBB end point");
MachineFunction *MF = A->getParent();
// We may need to update A's terminator, but we can't do that if AnalyzeBranch
// fails. If A uses a jump table, we won't touch it.
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
MachineBasicBlock *TBB = 0, *FBB = 0;
SmallVector<MachineOperand, 4> Cond;
if (TII->AnalyzeBranch(*A, TBB, FBB, Cond))
return NULL;
++NumSplits;
MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
MF->insert(llvm::next(MachineFunction::iterator(A)), NMBB);
DEBUG(dbgs() << "PHIElimination splitting critical edge:"
" BB#" << A->getNumber()
<< " -- BB#" << NMBB->getNumber()
<< " -- BB#" << B->getNumber() << '\n');
A->ReplaceUsesOfBlockWith(B, NMBB);
A->updateTerminator();
// Insert unconditional "jump B" instruction in NMBB if necessary.
NMBB->addSuccessor(B);
if (!NMBB->isLayoutSuccessor(B)) {
Cond.clear();
MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond);
}
// Fix PHI nodes in B so they refer to NMBB instead of A
for (MachineBasicBlock::iterator i = B->begin(), e = B->end();
i != e && i->isPHI(); ++i)
for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
if (i->getOperand(ni+1).getMBB() == A)
i->getOperand(ni+1).setMBB(NMBB);
if (LiveVariables *LV=getAnalysisIfAvailable<LiveVariables>())
LV->addNewBlock(NMBB, A, B);
if (MachineDominatorTree *MDT=getAnalysisIfAvailable<MachineDominatorTree>())
MDT->addNewBlock(NMBB, A);
return NMBB;
}
/// estimateRSStackSizeLimit - Look at each instruction that references stack
/// frames and return the stack size limit beyond which some of these
/// instructions will require a scratch register during their expansion later.
// FIXME: Move to TII?
static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
const TargetFrameLowering *TFI) {
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned Limit = (1 << 12) - 1;
for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
I != E; ++I) {
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
if (!I->getOperand(i).isFI()) continue;
// When using ADDri to get the address of a stack object, 255 is the
// largest offset guaranteed to fit in the immediate offset.
if (I->getOpcode() == ARM::ADDri) {
Limit = std::min(Limit, (1U << 8) - 1);
break;
}
// Otherwise check the addressing mode.
switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
case ARMII::AddrMode3:
case ARMII::AddrModeT2_i8:
Limit = std::min(Limit, (1U << 8) - 1);
break;
case ARMII::AddrMode5:
case ARMII::AddrModeT2_i8s4:
Limit = std::min(Limit, ((1U << 8) - 1) * 4);
break;
case ARMII::AddrModeT2_i12:
// i12 supports only positive offset so these will be converted to
// i8 opcodes. See llvm::rewriteT2FrameIndex.
if (TFI->hasFP(MF) && AFI->hasStackFrame())
Limit = std::min(Limit, (1U << 8) - 1);
break;
case ARMII::AddrMode4:
case ARMII::AddrMode6:
// Addressing modes 4 & 6 (load/store) instructions can't encode an
// immediate offset for stack references.
return 0;
default:
break;
}
break; // At most one FI per instruction
}
}
}
return Limit;
}
bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
bool &sawLoad,
bool &sawStore,
SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses) {
if (candidate->isImplicitDef() || candidate->isKill())
return true;
// Loads or stores cannot be moved past a store to the delay slot
// and stores cannot be moved past a load.
if (candidate->mayLoad()) {
if (sawStore)
return true;
sawLoad = true;
}
if (candidate->mayStore()) {
if (sawStore)
return true;
sawStore = true;
if (sawLoad)
return true;
}
assert((!candidate->isCall() && !candidate->isReturn()) &&
"Cannot put calls or returns in delay slot.");
for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
const MachineOperand &MO = candidate->getOperand(i);
unsigned Reg;
if (!MO.isReg() || !(Reg = MO.getReg()))
continue; // skip
if (MO.isDef()) {
// check whether Reg is defined or used before delay slot.
if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
return true;
}
if (MO.isUse()) {
// check whether Reg is defined before delay slot.
if (IsRegInSet(RegDefs, Reg))
return true;
}
}
return false;
}
/// calculateCallsInformation - Calculate the MaxCallFrameSize and HasCalls
/// variables for the function's frame information and eliminate call frame
/// pseudo instructions.
void PEI::calculateCallsInformation(MachineFunction &Fn) {
const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
unsigned MaxCallFrameSize = 0;
bool HasCalls = false;
// Get the function call frame set-up and tear-down instruction opcode
int FrameSetupOpcode = RegInfo->getCallFrameSetupOpcode();
int FrameDestroyOpcode = RegInfo->getCallFrameDestroyOpcode();
// Early exit for targets which have no call frame setup/destroy pseudo
// instructions.
if (FrameSetupOpcode == -1 && FrameDestroyOpcode == -1)
return;
std::vector<MachineBasicBlock::iterator> FrameSDOps;
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I)
if (I->getOpcode() == FrameSetupOpcode ||
I->getOpcode() == FrameDestroyOpcode) {
assert(I->getNumOperands() >= 1 && "Call Frame Setup/Destroy Pseudo"
" instructions should have a single immediate argument!");
unsigned Size = I->getOperand(0).getImm();
if (Size > MaxCallFrameSize) MaxCallFrameSize = Size;
HasCalls = true;
FrameSDOps.push_back(I);
} else if (I->getOpcode() == TargetInstrInfo::INLINEASM) {
// An InlineAsm might be a call; assume it is to get the stack frame
// aligned correctly for calls.
HasCalls = true;
}
MachineFrameInfo *FFI = Fn.getFrameInfo();
FFI->setHasCalls(HasCalls);
FFI->setMaxCallFrameSize(MaxCallFrameSize);
for (std::vector<MachineBasicBlock::iterator>::iterator
i = FrameSDOps.begin(), e = FrameSDOps.end(); i != e; ++i) {
MachineBasicBlock::iterator I = *i;
// If call frames are not being included as part of the stack frame, and
// there is no dynamic allocation (therefore referencing frame slots off
// sp), leave the pseudo ops alone. We'll eliminate them later.
if (RegInfo->hasReservedCallFrame(Fn) || RegInfo->hasFP(Fn))
RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
}
}
/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
/// variables that are live out of DomBB will be marked as passing live through
/// BB.
void LiveVariables::addNewBlock(MachineBasicBlock *BB,
MachineBasicBlock *DomBB,
MachineBasicBlock *SuccBB) {
const unsigned NumNew = BB->getNumber();
SmallSet<unsigned, 16> Defs, Kills;
MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
for (; BBI != BBE && BBI->isPHI(); ++BBI) {
// Record the def of the PHI node.
Defs.insert(BBI->getOperand(0).getReg());
// All registers used by PHI nodes in SuccBB must be live through BB.
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
if (BBI->getOperand(i+1).getMBB() == BB)
getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
}
// Record all vreg defs and kills of all instructions in SuccBB.
for (; BBI != BBE; ++BBI) {
for (MachineInstr::mop_iterator I = BBI->operands_begin(),
E = BBI->operands_end(); I != E; ++I) {
if (I->isReg() && TargetRegisterInfo::isVirtualRegister(I->getReg())) {
if (I->isDef())
Defs.insert(I->getReg());
else if (I->isKill())
Kills.insert(I->getReg());
}
}
}
// Update info for all live variables
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
// If the Defs is defined in the successor it can't be live in BB.
if (Defs.count(Reg))
continue;
// If the register is either killed in or live through SuccBB it's also live
// through BB.
VarInfo &VI = getVarInfo(Reg);
if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
VI.AliveBlocks.set(NumNew);
}
}
/// PropagateForward - Traverse forward and look for the kill of OldReg. If
/// it can successfully update all of the uses with NewReg, do so and
/// return true.
bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
MachineBasicBlock *MBB,
unsigned OldReg, unsigned NewReg) {
if (MII == MBB->end())
return false;
SmallVector<MachineOperand*, 4> Uses;
while (++MII != MBB->end()) {
bool FoundKill = false;
const TargetInstrDesc &TID = MII->getDesc();
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MII->getOperand(i);
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
continue;
if (Reg == OldReg) {
if (MO.isDef() || MO.isImplicit())
return false;
// Abort the use is actually a sub-register use. We don't have enough
// information to figure out if it is really legal.
if (MO.getSubReg())
return false;
const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
if (RC && !RC->contains(NewReg))
return false;
if (MO.isKill())
FoundKill = true;
Uses.push_back(&MO);
} else if (TRI->regsOverlap(Reg, NewReg) ||
TRI->regsOverlap(Reg, OldReg))
return false;
}
if (FoundKill) {
for (unsigned i = 0, e = Uses.size(); i != e; ++i)
Uses[i]->setReg(NewReg);
return true;
}
}
return false;
}
bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
bool &sawLoad,
bool &sawStore,
SmallSet<unsigned, 32> &RegDefs,
SmallSet<unsigned, 32> &RegUses)
{
if (candidate->isImplicitDef() || candidate->isKill())
return true;
if (candidate->mayLoad()) {
sawLoad = true;
if (sawStore)
return true;
}
if (candidate->mayStore()) {
if (sawStore)
return true;
sawStore = true;
if (sawLoad)
return true;
}
for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
const MachineOperand &MO = candidate->getOperand(i);
if (!MO.isReg())
continue; // skip
unsigned Reg = MO.getReg();
if (MO.isDef()) {
//check whether Reg is defined or used before delay slot.
if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
return true;
}
if (MO.isUse()) {
//check whether Reg is defined before delay slot.
if (IsRegInSet(RegDefs, Reg))
return true;
}
}
return false;
}
MachineBasicBlock::iterator Z80FrameLowering::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
//if (!hasReservedCallFrame(MF)) {
unsigned Amount = TII.getFrameSize(*I);
unsigned ScratchReg = I->getOperand(I->getNumOperands() - 1).getReg();
assert((Z80::A24RegClass.contains(ScratchReg) ||
Z80::A16RegClass.contains(ScratchReg)) &&
"Expected last operand to be the scratch reg.");
if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
Amount -= TII.getFramePoppedByCallee(*I);
assert(TargetRegisterInfo::isPhysicalRegister(ScratchReg) &&
"Reg alloc should have already happened.");
BuildStackAdjustment(MF, MBB, I, I->getDebugLoc(), ScratchReg, Amount);
}
//}
return MBB.erase(I);
}
//Insert Defs and Uses of MI into the sets RegDefs and RegUses.
void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
SmallSet<unsigned, 32>& RegDefs,
SmallSet<unsigned, 32>& RegUses)
{
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
continue;
if (MO.isDef())
RegDefs.insert(Reg);
if (MO.isUse())
RegUses.insert(Reg);
}
}
/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
/// variables that are live out of DomBB will be marked as passing live through
/// BB.
void LiveVariables::addNewBlock(MachineBasicBlock *BB,
MachineBasicBlock *DomBB,
MachineBasicBlock *SuccBB) {
const unsigned NumNew = BB->getNumber();
// All registers used by PHI nodes in SuccBB must be live through BB.
for (MachineBasicBlock::iterator BBI = SuccBB->begin(),
BBE = SuccBB->end(); BBI != BBE && BBI->isPHI(); ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
if (BBI->getOperand(i+1).getMBB() == BB)
getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
// Update info for all live variables
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
VarInfo &VI = getVarInfo(Reg);
if (!VI.AliveBlocks.test(NumNew) && VI.isLiveIn(*SuccBB, Reg, *MRI))
VI.AliveBlocks.set(NumNew);
}
}
/// ReplaceUsesOfBlockWith - Given a machine basic block that branched to
/// 'Old', change the code and CFG so that it branches to 'New' instead.
void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
MachineBasicBlock *New) {
assert(Old != New && "Cannot replace self with self!");
MachineBasicBlock::iterator I = end();
while (I != begin()) {
--I;
if (!I->getDesc().isTerminator()) break;
// Scan the operands of this machine instruction, replacing any uses of Old
// with New.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isMBB() &&
I->getOperand(i).getMBB() == Old)
I->getOperand(i).setMBB(New);
}
// Update the successor information.
replaceSuccessor(Old, New);
}
void
MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
if (this == fromMBB)
return;
while (!fromMBB->succ_empty()) {
MachineBasicBlock *Succ = *fromMBB->succ_begin();
addSuccessor(Succ);
fromMBB->removeSuccessor(Succ);
// Fix up any PHI nodes in the successor.
for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
MI != ME && MI->isPHI(); ++MI)
for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
MachineOperand &MO = MI->getOperand(i);
if (MO.getMBB() == fromMBB)
MO.setMBB(this);
}
}
}
bool MOVToLEAPass::runOnMachineFunction(MachineFunction &Fn) {
const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
bool Changed = false;
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) {
++PreMOVtoLEAInstructionCount;
if (I->getNumOperands() != 2 ||
!I->getOperand(0).isReg() || !I->getOperand(1).isReg()) {
++I;
continue;
}
unsigned leaOpc;
if (I->getOpcode() == X86::MOV32rr) {
leaOpc = X86::LEA32r;
} else if (I->getOpcode() == X86::MOV64rr) {
leaOpc = X86::LEA64r;
} else {
++I;
continue;
}
unsigned int Roll = RandomNumberGenerator::Generator().Random(100);
++MOVCandidates;
if (Roll >= multicompiler::getFunctionOption(
multicompiler::MOVToLEAPercentage, *Fn.getFunction())) {
++I;
continue;
}
++ReplacedMOV;
MachineBasicBlock::iterator J = I;
++I;
addRegOffset(BuildMI(*BB, J, J->getDebugLoc(),
TII->get(leaOpc), J->getOperand(0).getReg()),
J->getOperand(1).getReg(), false, 0);
J->eraseFromParent();
Changed = true;
}
return Changed;
}
void SIInsertWaits::handleSendMsg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) {
if (ST->getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
return;
// There must be "S_NOP 0" between an instruction writing M0 and S_SENDMSG.
if (LastInstWritesM0 && I->getOpcode() == AMDGPU::S_SENDMSG) {
BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP)).addImm(0);
LastInstWritesM0 = false;
return;
}
// Set whether this instruction sets M0
LastInstWritesM0 = false;
unsigned NumOperands = I->getNumOperands();
for (unsigned i = 0; i < NumOperands; i++) {
const MachineOperand &Op = I->getOperand(i);
if (Op.isReg() && Op.isDef() && Op.getReg() == AMDGPU::M0)
LastInstWritesM0 = true;
}
}
// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
SmallSet<unsigned, 32>& RegDefs,
SmallSet<unsigned, 32>& RegUses)
{
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0)
continue;
if (MO.isDef())
RegDefs.insert(Reg);
if (MO.isUse()) {
// Implicit register uses of retl are return values and
// retl does not use them.
if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
continue;
RegUses.insert(Reg);
}
}
}