Nodecl::NodeclVisitor<void>::Ret AVX2StrideVisitorConv::unhandled_node(const Nodecl::NodeclBase& node) { //printf("Unsupported %d: %s\n", _vector_num_elements, node.prettyprint().c_str()); if (node.get_type().is_vector()) { Nodecl::NodeclBase new_node = node.shallow_copy().as<Nodecl::NodeclBase>(); new_node.set_type(TL::Type::get_int_type().get_vector_of_elements( _vector_num_elements)); // TODO better node.replace(new_node); Nodecl::NodeclBase::Children children = node.children(); for(Nodecl::NodeclBase::Children::iterator it = children.begin(); it != children.end(); it ++) { walk(*it); } } return Ret(); }
void DeviceFPGA::add_hls_pragmas( Nodecl::NodeclBase &task, TL::ObjectList<OutlineDataItem*> &data_items ) { /* * Insert hls pragmas in order to denerate input/output connections * Every parameter needs a directive: * scalar: create plain wire connections: * #pragma HLS INTERFACE ap_none port=VAR * #pragma AP resource core=AXI_SLAVE variable=VAR metadata="-bus_bundle AXIlite" * * Array; create fifo port to be handled by axi stream * #pragma HLS stream variable=VAR <-- NOT NEEDED * #pragma HLS resource core=AXI4Stream variable=VAR * #pragma HLS interface ap_fifo port=VAR * * For every task there is a control bus defined to kick the accelerator off: * * #pragma AP resource core=AXI_SLAVE variable=return metadata="-bus_bundle AXIlite" \ * port_map={{ap_start START} {ap_done DONE} {ap_idle IDLE} {ap_return RETURN}} * * All of this stuff must be inside the function body i.e. * * void foo(...) * { * pragma stuff * function body * } * */ //see what kind of ast it really is std::cerr << ast_node_type_name(task.get_kind()) << " in_list: " << task.is_in_list() << " locus: " << task.get_locus() << std::endl; //Dig into the tree and find where the function statements are ObjectList<Nodecl::NodeclBase> tchildren = task.children(); Nodecl::NodeclBase& context = tchildren.front(); ObjectList<Nodecl::NodeclBase> cchildren = context.children(); Nodecl::List list(cchildren.front().get_internal_nodecl()); Nodecl::List stlist(list.begin()->children().front().get_internal_nodecl()); Nodecl::UnknownPragma ctrl_bus = Nodecl::UnknownPragma::make( "AP resource core=AXI_SLAVE variable=return metadata=\"-bus_bundle AXIlite\" port_map={{ap_start START} {ap_done DONE} {ap_idle IDLE} {ap_return RETURN}}"); stlist.prepend(ctrl_bus); //since we are using prepend, everything is going to appar in reverse order //but this may not be a real issue // TL::ObjectList<OutlineDataItem*> data_items = outline_info.get_data_items(); for (TL::ObjectList<OutlineDataItem*>::iterator it = data_items.begin(); it != data_items.end(); it++) { std::string field_name = (*it)->get_field_name(); Nodecl::UnknownPragma pragma_node; if ((*it)->get_copies().empty()) { //set scalar argumenit pragmas pragma_node = Nodecl::UnknownPragma::make("HLS INTERFACE ap_none port=" + field_name); stlist.prepend(pragma_node); pragma_node = Nodecl::UnknownPragma::make("AP resource core=AXI_SLAVE variable=" + field_name + " metadata=\"-bus_bundle AXIlite\""); stlist.prepend(pragma_node); } else { //set array/stream pragmas pragma_node = Nodecl::UnknownPragma::make( "HLS resource core=AXI4Stream variable=" + field_name); stlist.prepend(pragma_node); pragma_node = Nodecl::UnknownPragma::make( "HLS interface ap_fifo port=" + field_name); stlist.prepend(pragma_node); } } }