virtual bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
tlm::tlm_dmi& dmi_data)
{
// Permit read and write access
dmi_data.allow_read_write();
// Set other details of DMI region
dmi_data.set_dmi_ptr( reinterpret_cast<unsigned char*>( &mem[0] ) );
dmi_data.set_start_address( 0 );
dmi_data.set_end_address( SIZE*4-1 );
dmi_data.set_read_latency( LATENCY );
dmi_data.set_write_latency( LATENCY );
return true;
}
bool
lt_dmi_target::get_direct_mem_ptr
( tlm::tlm_generic_payload &gp ///< address + extensions
, tlm::tlm_dmi &dmi_properties ///< dmi data
)
{
std::ostringstream msg;
msg.str("");
sc_dt::uint64 address = gp.get_address();
// First check to see if we are "open" to a dmi
if(!m_dmi_enabled)
{
msg << "Target: " << m_ID
<< " DMI not enabled, not expecting call ";
REPORT_INFO(filename, __FUNCTION__, msg.str());
}
else
{ // dmi processing
if (address < m_end_address+1) // check that address is in our range
{
// set up dmi properties object ======================================
dmi_properties.allow_read_write ( );
dmi_properties.set_start_address ( m_start_address );
dmi_properties.set_end_address ( m_end_address );
dmi_properties.set_dmi_ptr ( m_target_memory.get_mem_ptr () );
dmi_properties.set_read_latency ( m_read_response_delay );
dmi_properties.set_write_latency ( m_write_response_delay );
msg << "Target: " << m_ID
<< " passing DMI pointer back to initiator";
REPORT_INFO(filename, __FUNCTION__, msg.str());
return true;
}
else
{
msg << "Target: " << m_ID
<< " DMI pointer request for address= " << address
<< " max address for this target = " << m_end_address+1;
REPORT_INFO(filename, __FUNCTION__, msg.str());
} // end else
} // end else
return false;
} // end get_direct_mem_ptr
