void TR::ARM64MemSrc1Instruction::assignRegisters(TR_RegisterKinds kindToBeAssigned)
{
TR::Machine *machine = cg()->machine();
TR::MemoryReference *mref = getMemoryReference();
TR::Register *sourceVirtual = getSource1Register();
if (getDependencyConditions())
getDependencyConditions()->assignPostConditionRegisters(this, kindToBeAssigned, cg());
sourceVirtual->block();
mref->assignRegisters(this, cg());
sourceVirtual->unblock();
mref->blockRegisters();
TR::RealRegister *assignedRegister = sourceVirtual->getAssignedRealRegister();
if (assignedRegister == NULL)
{
assignedRegister = machine->assignOneRegister(this, sourceVirtual);
}
mref->unblockRegisters();
setSource1Register(assignedRegister);
if (getDependencyConditions())
getDependencyConditions()->assignPreConditionRegisters(this->getPrev(), kindToBeAssigned, cg());
}
void TR::ARM64Trg1MemInstruction::assignRegisters(TR_RegisterKinds kindToBeAssigned)
{
TR::Machine *machine = cg()->machine();
TR::MemoryReference *mref = getMemoryReference();
TR::Register *targetVirtual = getTargetRegister();
if (getDependencyConditions())
getDependencyConditions()->assignPostConditionRegisters(this, kindToBeAssigned, cg());
mref->blockRegisters();
setTargetRegister(machine->assignOneRegister(this, targetVirtual));
mref->unblockRegisters();
targetVirtual->block();
mref->assignRegisters(this, cg());
targetVirtual->unblock();
if (getDependencyConditions())
getDependencyConditions()->assignPreConditionRegisters(this->getPrev(), kindToBeAssigned, cg());
}