/***************************************************************************//** * @brief Initializes the device and powers-up all channels. The device is * initialized with the values held by AD5755_InitialSettings structure. * * @param device - The device structure. * @param init_param - The structure that contains the device initial * parameters. * * @return status - Result of the initialization procedure. * Example: -1 - SPI peripheral was not initialized. * 0 - SPI peripheral is initialized. *******************************************************************************/ int8_t ad5755_init(struct ad5755_dev **device, struct ad5755_init_param init_param) { struct ad5755_dev *dev; uint8_t status; uint8_t channel = 0; uint16_t dac_control_buff[4] = {0, 0, 0, 0}; dev = (struct ad5755_dev *)malloc(sizeof(*dev)); if (!dev) return -1; dev->p_ad5755_st = &AD5755_st; dev->this_device = init_param.this_device; /* GPIO */ status = gpio_get(&dev->gpio_ldac, init_param.gpio_ldac); status |= gpio_get(&dev->gpio_rst, init_param.gpio_rst); status |= gpio_get(&dev->gpio_clr, init_param.gpio_clr); status |= gpio_get(&dev->gpio_poc, init_param.gpio_poc); /* GPIO configuration. */ AD5755_LDAC_OUT; AD5755_LDAC_LOW; AD5755_RESET_OUT; AD5755_RESET_HIGH; AD5755_CLEAR_OUT; AD5755_CLEAR_LOW; AD5755_POC_OUT; AD5755_POC_LOW; status |= spi_init(&dev->spi_desc, &init_param.spi_init); /* Device Setup. */ /* Configure the POC bit, STATREAD bit and ShtCcLim bit. */ ad5755_set_control_registers(dev, AD5755_CREG_MAIN, 0, (dev->p_ad5755_st->poc_bit * AD5755_MAIN_POC) | (dev->p_ad5755_st->stat_readbit * AD5755_MAIN_STATREAD) | AD5755_MAIN_SHTCCTLIM(dev->p_ad5755_st->sht_cc_lim_bit)); ad5755_software_reset(dev); mdelay(100); /* DC-to-DC configuration. */ ad5755_set_control_registers(dev, AD5755_CREG_DC_DC, 0, (dev->p_ad5755_st->dc_dc_comp_bit * AD5755_DC_DC_COMP) | (AD5755_DC_DC_FREQ(dev->p_ad5755_st->dc_dc_freq_bit)) | (AD5755_DC_DC_PHASE(dev->p_ad5755_st->dc_dc_phase_bit)) | (AD5755_DC_DC_MAX_V(dev->p_ad5755_st->dc_dc_max_vbit))); /* Configure the DAC control register on a per channel basis. */ for(channel = AD5755_DAC_A; channel <= AD5755_DAC_D; channel++) { if((dev->this_device == ID_AD5755) || (dev->this_device == ID_AD5755_1)) { dac_control_buff[channel] = AD5755_DAC_INT_ENABLE | AD5755_DAC_CLR_EN | dev->p_ad5755_st->rset_bits[channel] | AD5755_DAC_DC_DC | dev->p_ad5755_st->ovrng_bits[channel] | AD5755_DAC_R(AD5755_R_0_5_V); } else { dac_control_buff[channel] = AD5755_DAC_INT_ENABLE | AD5755_DAC_CLR_EN | dev->p_ad5755_st->rset_bits[channel] | AD5755_DAC_DC_DC | dev->p_ad5755_st->ovrng_bits[channel] | AD5755_DAC_R(AD5755_R_4_20_MA); } ad5755_set_control_registers(dev, AD5755_CREG_DAC, channel, dac_control_buff[channel]); } /* Allow at least 200us before enabling the channel output. */ mdelay(200); /* Enable the channel output. */ for(channel = AD5755_DAC_A; channel <= AD5755_DAC_D; channel++) { /* Write to each DAC data register*/ ad5755_set_register_value(dev, AD5755_DREG_WR_DAC, channel, 0x0000); ad5755_set_control_registers(dev, AD5755_CREG_DAC, channel, dac_control_buff[channel] | AD5755_DAC_OUTEN); } *device = dev; return status; }
/***************************************************************************//** * @brief Initializes the device and powers-up all channels. The device is * initialized with the values held by AD5755_InitialSettings structure. * * @return status - Result of the initialization procedure. * Example: -1 - SPI peripheral was not initialized. * 0 - SPI peripheral is initialized. *******************************************************************************/ char AD5755_Init(AD5755_type_t device) { unsigned char status = -1; unsigned char channel = 0; AD5755_Setup *pAD5755_st = &AD5755_st; unsigned short dacControlBuff[4] = {0, 0, 0, 0}; this_device = device; /* GPIO configuration. */ AD5755_LDAC_OUT; AD5755_LDAC_LOW; AD5755_RESET_OUT; AD5755_RESET_HIGH; AD5755_CLEAR_OUT; AD5755_CLEAR_LOW; AD5755_POC_OUT; AD5755_POC_LOW; status = SPI_Init(0, // Transfer format. 8000000, // SPI clock frequency. 1, // SPI clock polarity. 1); // SPI clock edge. /* Device Setup. */ /* Configure the POC bit, STATREAD bit and ShtCcLim bit. */ AD5755_SetControlRegisters(AD5755_CREG_MAIN, 0, (pAD5755_st->pocBit * AD5755_MAIN_POC) | (pAD5755_st->statReadBit * AD5755_MAIN_STATREAD) | AD5755_MAIN_SHTCCTLIM(pAD5755_st->shtCcLimBit)); AD5755_Software_Reset(); TIME_DelayUs(100); /* DC-to-DC configuration. */ AD5755_SetControlRegisters(AD5755_CREG_DC_DC, 0, (pAD5755_st->dcDcCompBit * AD5755_DC_DC_COMP) | (AD5755_DC_DC_FREQ(pAD5755_st->dcDcFreqBit)) | (AD5755_DC_DC_PHASE(pAD5755_st->dcDcPhaseBit)) | (AD5755_DC_DC_MAX_V(pAD5755_st->dcDcMaxVBit))); /* Configure the DAC control register on a per channel basis. */ for(channel = AD5755_DAC_A; channel <= AD5755_DAC_D; channel++) { if((this_device == ID_AD5755) || (this_device == ID_AD5755_1)) { dacControlBuff[channel] = AD5755_DAC_INT_ENABLE | AD5755_DAC_CLR_EN | pAD5755_st->rsetBits[channel] | AD5755_DAC_DC_DC | pAD5755_st->ovrngBits[channel] | AD5755_DAC_R(AD5755_R_0_5_V); } else { dacControlBuff[channel] = AD5755_DAC_INT_ENABLE | AD5755_DAC_CLR_EN | pAD5755_st->rsetBits[channel] | AD5755_DAC_DC_DC | pAD5755_st->ovrngBits[channel] | AD5755_DAC_R(AD5755_R_4_20_MA); } AD5755_SetControlRegisters(AD5755_CREG_DAC, channel, dacControlBuff[channel]); } /* Allow at least 200us before enabling the channel output. */ TIME_DelayUs(200); /* Enable the channel output. */ for(channel = AD5755_DAC_A; channel <= AD5755_DAC_D; channel++) { /* Write to each DAC data register*/ AD5755_SetRegisterValue(AD5755_DREG_WR_DAC, channel, 0x0000); AD5755_SetControlRegisters(AD5755_CREG_DAC, channel, dacControlBuff[channel] | AD5755_DAC_OUTEN); } return status; }