/* ------------------------------------------------- */
int uda1380_write_reg(unsigned char reg, unsigned short value);
unsigned short uda1380_regs[0x30];
short uda1380_balance;
short uda1380_volume;
/* Definition of a playback configuration to start with */
#define NUM_DEFAULT_REGS 13
unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] =
{
REG_0, EN_DAC | EN_INT | EN_DEC | SYSCLK_256FS | WSPLL_25_50,
REG_I2S, I2S_IFMT_IIS,
REG_PWR, PON_PLL | PON_BIAS, /* PON_HP & PON_DAC is enabled later */
REG_AMIX, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f), /* 00=max, 3f=mute */
REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20), /* 00=max, ff=mute */
REG_MIX_VOL, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff), /* 00=max, ff=mute */
REG_EQ, EQ_MODE_MAX, /* Bass and tremble = 0 dB */
REG_MUTE, MUTE_MASTER | MUTE_CH2, /* Mute everything to start with */
REG_MIX_CTL, MIX_CTL_MIX, /* Enable mixer */
REG_DEC_VOL, 0,
REG_PGA, MUTE_ADC,
REG_ADC, SKIP_DCFIL,
REG_AGC, 0
};
/* Returns 0 if register was written or -1 if write failed */
int uda1380_write_reg(unsigned char reg, unsigned short value)
short recgain_line;
/* Definition of a playback configuration to start with */
#define NUM_DEFAULT_REGS 13
unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] =
{
REG_0, EN_DAC | EN_INT | EN_DEC |
#ifdef USE_WSPLL
ADC_CLK | DAC_CLK | WSPLL_25_50 |
#endif
SYSCLK_256FS,
REG_I2S, I2S_IFMT_IIS,
REG_PWR, PON_PLL | PON_BIAS,
/* PON_HP & PON_DAC is enabled later */
REG_AMIX, AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f),
/* 00=max, 3f=mute */
REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20),
/* 00=max, ff=mute */
REG_MIX_VOL, MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff),
/* 00=max, ff=mute */
REG_EQ, EQ_MODE_MAX,
/* Bass and treble = 0 dB */
REG_MUTE, MUTE_MASTER | MUTE_CH2,
/* Mute everything to start with */
REG_MIX_CTL, MIX_CTL_MIX,
/* Enable mixer */
REG_DEC_VOL, 0,
REG_PGA, MUTE_ADC,
REG_ADC, SKIP_DCFIL,
REG_AGC, 0