void
ar9287_1_3_enable_async_fifo(struct athn_softc *sc)
{
/* Enable ASYNC FIFO. */
AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
AR_CLRBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
AR_WRITE_BARRIER(sc);
}
void
ar9380_init_swreg(struct athn_softc *sc)
{
const struct ar9380_eeprom *eep = sc->eep;
if (eep->baseEepHeader.featureEnable & AR_EEP_INTERNAL_REGULATOR) {
/* Internal regulator is ON. */
AR_CLRBITS(sc, AR_RTC_REG_CONTROL1,
AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
AR_WRITE(sc, AR_RTC_REG_CONTROL0, eep->baseEepHeader.swreg);
AR_SETBITS(sc, AR_RTC_REG_CONTROL1,
AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
} else
AR_SETBITS(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_SWREG_PRD);
AR_WRITE_BARRIER(sc);
}
void
ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
const struct ar_spur_chan *spurchans;
int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd;
int spur_off, range, i;
/* NB: Always clear. */
AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
range = (extc != NULL) ? 19 : 10;
spurchans = sc->ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
spur = spurchans[i].spurChan;
if (spur == AR_NO_SPUR)
return; /* XXX disable if it was enabled! */
spur /= 10;
if (IEEE80211_IS_CHAN_2GHZ(c))
spur += AR_BASE_FREQ_2GHZ;
else
spur += AR_BASE_FREQ_5GHZ;
spur -= c->ic_freq;
if (abs(spur) < range)
break;
}
if (i == AR_EEPROM_MODAL_SPURS)
return; /* XXX disable if it was enabled! */
DPRINTFN(2, ("enabling spur mitigation\n"));
AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
AR_WRITE(sc, AR_PHY_SPUR_REG,
AR_PHY_SPUR_REG_MASK_RATE_CNTL |
AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
AR_PHY_SPUR_REG_MASK_RATE_SELECT |
AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
#ifndef IEEE80211_NO_HT
if (extc != NULL) {
spur_delta_phase = (spur * 262144) / 10;
if (spur < 0) {
spur_subchannel_sd = 1;
spur_off = spur + 10;
} else {
spur_subchannel_sd = 0;
spur_off = spur - 10;
}
} else
#endif
{
spur_delta_phase = (spur * 524288) / 10;
spur_subchannel_sd = 0;
spur_off = spur;
}
if (IEEE80211_IS_CHAN_2GHZ(c))
spur_freq_sd = (spur_off * 2048) / 44;
else
spur_freq_sd = (spur_off * 2048) / 40;
AR_WRITE(sc, AR_PHY_TIMING11,
AR_PHY_TIMING11_USE_SPUR_IN_AGC |
SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
AR_WRITE(sc, AR_PHY_SFCORR_EXT,
SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
AR_WRITE_BARRIER(sc);
bin = spur * 320;
ar5008_set_viterbi_mask(sc, bin);
}
void
ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
const struct ar9380_eeprom *eep = sc->eep;
const uint8_t *spurchans;
uint32_t reg;
int idx, spur_delta_phase, spur_off, range, i;
int freq, spur, spur_freq_sd, spur_subchannel_sd;
if (IEEE80211_IS_CHAN_2GHZ(c))
spurchans = eep->modalHeader2G.spurChans;
else
spurchans = eep->modalHeader5G.spurChans;
if (spurchans[0] == 0)
return;
/* Disable OFDM spur mitigation. */
AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
reg = AR_READ(sc, AR_PHY_TIMING11);
reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
AR_WRITE(sc, AR_PHY_TIMING11, reg);
AR_CLRBITS(sc, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD);
AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
reg = AR_READ(sc, AR_PHY_SPUR_REG);
reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
reg &= ~AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
reg &= ~AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
reg &= ~AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
AR_WRITE_BARRIER(sc);
freq = c->ic_freq;
#ifndef IEEE80211_NO_HT
if (extc != NULL) {
range = 19; /* +/- 19MHz range. */
if (AR_READ(sc, AR_PHY_GEN_CTRL) & AR_PHY_GC_DYN2040_PRI_CH)
freq += 10;
else
freq -= 10;
} else
#endif
range = 10; /* +/- 10MHz range. */
for (i = 0; i < AR9380_EEPROM_MODAL_SPURS; i++) {
spur = spurchans[i];
if (spur == 0)
return;
/* Convert to frequency. */
if (IEEE80211_IS_CHAN_2GHZ(c))
spur = 2300 + spur;
else
spur = 4900 + (spur * 5);
spur -= freq;
if (abs(spur) < range)
break;
}
if (i == AR9380_EEPROM_MODAL_SPURS)
return;
/* Enable OFDM spur mitigation. */
#ifndef IEEE80211_NO_HT
if (extc != NULL) {
spur_delta_phase = (spur * 131072) / 5;
reg = AR_READ(sc, AR_PHY_GEN_CTRL);
if (spur < 0) {
spur_subchannel_sd =
(reg & AR_PHY_GC_DYN2040_PRI_CH) == 0;
spur_off = spur + 10;
} else {
spur_subchannel_sd =
(reg & AR_PHY_GC_DYN2040_PRI_CH) != 0;
spur_off = spur - 10;
}
} else
#endif
{
spur_delta_phase = (spur * 262144) / 5;
spur_subchannel_sd = 0;
spur_off = spur;
}
spur_freq_sd = (spur_off * 512) / 11;
AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
reg = AR_READ(sc, AR_PHY_TIMING11);
reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
AR_WRITE(sc, AR_PHY_TIMING11, reg);
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
if (spur_subchannel_sd)
reg |= AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
else
reg &= ~AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
reg = AR_READ(sc, AR_PHY_SPUR_REG);
reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
reg = RW(reg, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
reg |= AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
if (AR_READ(sc, AR_PHY_MODE) & AR_PHY_MODE_DYNAMIC)
reg |= AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
reg |= AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
idx = (spur * 16) / 5;
if (idx < 0)
idx--;
/* Write pilot mask. */
AR_SETBITS(sc, AR_PHY_TIMING4,
AR_PHY_TIMING4_ENABLE_PILOT_MASK |
AR_PHY_TIMING4_ENABLE_CHAN_MASK);
reg = AR_READ(sc, AR_PHY_PILOT_SPUR_MASK);
reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0x0c);
AR_WRITE(sc, AR_PHY_PILOT_SPUR_MASK, reg);
reg = AR_READ(sc, AR_PHY_SPUR_MASK_A);
reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
AR_WRITE(sc, AR_PHY_SPUR_MASK_A, reg);
reg = AR_READ(sc, AR_PHY_CHAN_SPUR_MASK);
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c);
AR_WRITE(sc, AR_PHY_CHAN_SPUR_MASK, reg);
AR_WRITE_BARRIER(sc);
}
