/** * Initialize ASRC registers with a default configurations */ static int fsl_asrc_init(struct fsl_asrc *asrc_priv) { /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN); /* Disable interrupt by default */ regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0); /* Apply recommended settings for parameters from Reference Manual */ regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff); regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555); regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280); regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280); regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280); /* Base address for task queue FIFO. Set to 0x7C */ regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1, ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); /* Set the processing clock for 76KHz to 133M */ regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6); /* Set the processing clock for 56KHz to 133M */ return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947); }
static int mxc_init_asrc(void) { /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN); /* Disable interrupt by default */ regmap_write(asrc->regmap, REG_ASRIER, 0x0); /* Default 2: 6: 2 channel assignment */ regmap_update_bits(asrc->regmap, REG_ASRCNCR, ASRCNCR_ANCx_MASK(ASRC_PAIR_A, asrc->channel_bits), ASRCNCR_ANCx_set(ASRC_PAIR_A, 2, asrc->channel_bits)); regmap_update_bits(asrc->regmap, REG_ASRCNCR, ASRCNCR_ANCx_MASK(ASRC_PAIR_B, asrc->channel_bits), ASRCNCR_ANCx_set(ASRC_PAIR_B, 6, asrc->channel_bits)); regmap_update_bits(asrc->regmap, REG_ASRCNCR, ASRCNCR_ANCx_MASK(ASRC_PAIR_C, asrc->channel_bits), ASRCNCR_ANCx_set(ASRC_PAIR_C, 2, asrc->channel_bits)); /* Parameter Registers recommended settings */ regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff); regmap_write(asrc->regmap, REG_ASRPM2, 0x255555); regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280); regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280); regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280); /* Base address for task queue FIFO. Set to 0x7C */ regmap_update_bits(asrc->regmap, REG_ASRTFR1, ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); /* Set the processing clock for 76KHz, 133M */ regmap_write(asrc->regmap, REG_ASR76K, 0x06D6); /* Set the processing clock for 56KHz, 133M */ return regmap_write(asrc->regmap, REG_ASR56K, 0x0947); }