void RESET_TWI()
{
uint8 data = AT91C_BASE_TWI->TWI_RHR;
uint16 status = AT91C_BASE_TWI->TWI_SR;
// Configure TWI in master mode
AT91F_TWI_Configure (AT91C_BASE_TWI);
// Configure TWI PIOs
AT91F_TWI_CfgPIO();
AT91F_PIO_CfgOpendrain(AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA1_TWCK ) |
((unsigned int) AT91C_PA0_TWD ) );
// Configure PMC by enabling TWI clock
AT91F_TWI_CfgPMC ();
// AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1<<AT91C_ID_TWI ) ;
// Set TWI Clock Waveform Generator Register
AT91F_SetTwiClock();
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC,
AT91C_ID_TWI,
TWI_INTERRUPT_LEVEL,
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
( void (*)( void ) )AT91_TWI_ISR_ENTRY);
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TWI);
TWI_TransferStatus = FREE;
}
void TWI_init(void)
{
//* Reset peripheral
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_SWRST;
// Configure TWI PIOs
AT91F_TWI_CfgPIO ();
// Configure PMC by enabling TWI clock
AT91F_TWI_CfgPMC ();
// Configure TWI in master mode
AT91F_TWI_Configure (AT91C_BASE_TWI);
// Set TWI Clock Waveform Generator Register
AT91C_BASE_TWI->TWI_CWGR = 0x0000EDED;//0x0000EDED;
//* Disable interrupts
AT91C_BASE_TWI->TWI_IDR = (unsigned int) -1;
//TWI Interrupt
// Set protected mode and clear general mask.
//*AT91C_AIC_DCR = AT91C_AIC_DCR_PROT; //Enables protected mode
AT91C_BASE_AIC -> AIC_ICCR = AT91C_ID_TWI;
AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXRDY | AT91C_TWI_RXRDY;// | AT91C_TWI_TXCOMP | AT91C_TWI_NACK;
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_TWI, TWI_INTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE, TWI_c_irq_handler);
AT91F_AIC_DisableIt(AT91C_BASE_AIC, AT91C_ID_TWI);
return;
}
void AT91_IIC_init(void)
{
AT91F_TWI_CfgPIO ();
AT91F_PIO_CfgOpendrain(AT91C_BASE_PIOA, (unsigned int) AT91C_PA25_TWD);
// Configure PMC by enabling TWI clock
AT91F_TWI_CfgPMC ();
// Configure TWI in master mode
AT91F_TWI_Configure (AT91C_BASE_TWI);
// Set TWI Clock Waveform Generator Register
AT91F_SetTwiClock(AT91C_BASE_TWI);
}
//===============================================================================================
//*----------------------------------------------------------------------------
//* \fn AT91F_TWI_Open
//* \brief Initializes TWI device
//*----------------------------------------------------------------------------
void AT91F_TWI_Init(void)
{
TWI_QUEUE = xQueueCreate( 1, sizeof( unsigned int ) );
TWI_NACK_Error = ErrorCreate("TWI Nack");
TWI_TMO_Error = ErrorCreate("TWI TimeOut");
TWI_SEM_Error = ErrorCreate("TWI Access");
TWI_WriteData_Error = ErrorCreate("TWI Write");
TWI_OVRE_Error = ErrorCreate("TWI OVRE");
vSemaphoreCreateBinary( TWI_Semaphore );
while( TWI_QUEUE == 0 ) ; // Queue was not created and must not be used.
portENTER_CRITICAL();
{
// Configure TWI in master mode
AT91F_TWI_Configure (AT91C_BASE_TWI);
// Configure TWI PIOs
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, AT91C_PA1_TWCK );
AT91F_PIO_CfgOpendrain(AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA1_TWCK ) |
((unsigned int) AT91C_PA0_TWD ) );
AT91F_TWI_CfgPIO();
// Configure PMC by enabling TWI clock
AT91F_TWI_CfgPMC ();
// AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1<<AT91C_ID_TWI ) ;
// Set TWI Clock Waveform Generator Register
AT91F_SetTwiClock();
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC,
AT91C_ID_TWI,
TWI_INTERRUPT_LEVEL,
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
( void (*)( void ) )AT91_TWI_ISR_ENTRY);
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TWI);
TWI_TransferStatus = FREE;
}
portEXIT_CRITICAL();
}