示例#1
0
static void at91sam9g20ek_nand_hw_init(void)
{
	unsigned long csa;

	/* Enable CS3 */
	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA,
		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);

	/* Configure SMC CS3 for NAND/SmartMedia */
	at91_sys_write(AT91_SMC_SETUP(3),
		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(3),
		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
	at91_sys_write(AT91_SMC_CYCLE(3),
		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
	at91_sys_write(AT91_SMC_MODE(3),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
		       AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
		       AT91_SMC_DBW_8 |
#endif
		       AT91_SMC_TDF_(2));

	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);

	/* Configure RDY/BSY */
	at91_set_gpio_input(AT91_PIN_PC13, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(AT91_PIN_PC14, 1);
}
示例#2
0
static void at91cap9_nand_hw_init(void)
{
    unsigned long csa;

    /* Enable CS3 */
    csa = at91_sys_read(AT91_MATRIX_EBICSA);
    at91_sys_write(AT91_MATRIX_EBICSA,
                   csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
                   AT91_MATRIX_EBI_VDDIOMSEL_3_3V);

    /* Configure SMC CS3 for NAND/SmartMedia */
    at91_sys_write(AT91_SMC_SETUP(3),
                   AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
                   AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
    at91_sys_write(AT91_SMC_PULSE(3),
                   AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
                   AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
    at91_sys_write(AT91_SMC_CYCLE(3),
                   AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
    at91_sys_write(AT91_SMC_MODE(3),
                   AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
                   AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
                   AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
                   AT91_SMC_DBW_8 |
#endif
                   AT91_SMC_TDF_(1));

    at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);

    /* RDY/BSY is not connected */

    /* Enable NandFlash */
    at91_set_gpio_output(AT91_PIN_PD15, 1);
}
示例#3
0
void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
{
	/* Disable Watchdog */
	cfg->wdt_mr =
		AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
		AT91_WDT_WDV |
		AT91_WDT_WDDIS |
		AT91_WDT_WDD;

	/* define PDC[31:16] as DATA[31:16] */
	cfg->ebi_pio_pdr = 0xFFFF0000;
	/* no pull-up for D[31:16] */
	cfg->ebi_pio_ppudr = 0xFFFF0000;
	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
	cfg->ebi_csa =
		AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;

	cfg->smc_cs = 3;
	cfg->smc_mode =
		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		AT91_SMC_DBW_8 |
		AT91_SMC_EXNWMODE_DISABLE |
		AT91_SMC_TDF_(2);
	cfg->smc_cycle =
		AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5);
	cfg->smc_pulse =
		AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
		AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3);
	cfg->smc_setup =
		AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
		AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0);

	cfg->pmc_mor =
		AT91_PMC_MOSCEN |
		(255 << 8);		/* Main Oscillator Start-up Time */
	cfg->pmc_pllar =
		AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
		AT91_PMC_OUT |
		((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
	/* PCK/2 = MCK Master Clock from PLLA */
	cfg->pmc_mckr1 =
		AT91_PMC_CSS_SLOW |
		AT91_PMC_PRES_1 |
		AT91SAM9_PMC_MDIV_2 |
		AT91_PMC_PDIV_1;
	/* PCK/2 = MCK Master Clock from PLLA */
	cfg->pmc_mckr2 =
		AT91_PMC_CSS_PLLA |
		AT91_PMC_PRES_1 |
		AT91SAM9_PMC_MDIV_2 |
		AT91_PMC_PDIV_1;

	/* SDRAM */
	/* SDRAMC_TR - Refresh Timer register */
	cfg->sdrc_tr1 = 0x13C;
	/* SDRAMC_CR - Configuration register*/
	cfg->sdrc_cr =
		AT91_SDRAMC_NC_9 |
		AT91_SDRAMC_NR_13 |
		AT91_SDRAMC_NB_4 |
		AT91_SDRAMC_CAS_2 |
		AT91_SDRAMC_DBW_32 |
		(2 <<  8) |		/* Write Recovery Delay */
		(7 << 12) |		/* Row Cycle Delay */
		(2 << 16) |		/* Row Precharge Delay */
		(2 << 20) |		/* Row to Column Delay */
		(5 << 24) |		/* Active to Precharge Delay */
		(8 << 28);		/* Exit Self Refresh to Active Delay */

	/* Memory Device Register -> SDRAM */
	cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
	/* SDRAM_TR */
	cfg->sdrc_tr2 = (MASTER_CLOCK * 7);

	/* user reset enable */
	cfg->rstc_rmr =
		AT91_RSTC_KEY |
		AT91_RSTC_PROCRST |
		AT91_RSTC_RSTTYP_WAKEUP |
		AT91_RSTC_RSTTYP_WATCHDOG;
}
示例#4
0
static void __init ek_add_device_dm9000(void)
{
	/*
	 * Configure Chip-Select 2 on SMC for the DM9000.
	 * Note: These timings were calculated for MASTER_CLOCK = 100000000
	 *  according to the DM9000 timings.
	 */
	at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
	at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
	at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));

	/* Configure Reset signal as output */
	at91_set_gpio_output(AT91_PIN_PC10, 0);

	/* Configure Interrupt pin as input, no pull-up */
	at91_set_gpio_input(AT91_PIN_PC11, 0);

	platform_device_register(&at91sam9261_dm9000_device);
}
示例#5
0
/*
 * initialize the som-9g20 for apcc.
 */
static void apcc_init(void)
{
    unsigned int cnt = 10000;

    { /* initialize PCK1 - this is output to the FPGA as clock reference.
       * select PLLA as clock source (18.432 * 42) and div by 32
       * 24.192 mHz.
       */
	at91_sys_write(AT91_PMC_PCKR(1), AT91_PMC_CSS_PLLA | AT91_PMC_PRES_32);

	/* Enable PCK1 output */
	at91_sys_write(AT91_PMC_SCER, AT91_PMC_PCK1);

	/* Wait for PCK1 to come ready or timeout */
	while (cnt-- > 0) {
	    volatile unsigned long scsr = at91_sys_read(AT91_PMC_SCSR);
	    if ((scsr & AT91_PMC_PCK1RDY) != 0) {
		break;
	    }
	}

	/* configure PB31 to be used as PCK1 */
	at91_set_A_periph(AT91_PIN_PB31, 0);
    }

    { /* initialize sensys fpga */

	/*
	 * Configure CS0 (Chip Select 0) for FPGA (SMC @ FFFFEC00)
	 *
	 * SETUP - 0x1F3F1F3F
	 * PULSE - 0x403F403F
	 * CYCLE - 0x013E013E
	 * MODE  - 0x000F0003
	 */
	at91_sys_write(AT91_SMC_SETUP(0),
		       AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(4) |
		       AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(4));

	at91_sys_write(AT91_SMC_PULSE(0),
		       AT91_SMC_NWEPULSE_(20) | AT91_SMC_NCS_WRPULSE_(20) |
		       AT91_SMC_NRDPULSE_(22) | AT91_SMC_NCS_RDPULSE_(22));

	at91_sys_write(AT91_SMC_CYCLE(0),
		       AT91_SMC_NWECYCLE_(35) | AT91_SMC_NRDCYCLE_(29));

	at91_sys_write(AT91_SMC_MODE(0),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
		       AT91_SMC_DBW_8 |
		       AT91_SMC_TDF_(1));
    }

    {
	/* to conserve power, disable the AtoD of phy. 
	 */
        at91_set_gpio_output(AT91_PIN_PA22, 1);
    }

#ifdef CONFIG_HW_WATCHDOG
    {	/* set up watchdog port */
        at91_set_gpio_output(AT91_PIN_PB18, 1);
	WATCHDOG_RESET();
    }
#endif
}
示例#6
0
void __init at91_add_device_nand(struct at91_nand_data *data)
{
	unsigned long csa, mode;

	if (!data)
		return;

	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);

	if (cpu_is_at91sam9260()) {
		/* Timing for sam9260 */
		/* set the bus interface characteristics */
		at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
				| AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));

		at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
				| AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));

		at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));

		if (data->bus_width_16)
			mode = AT91_SMC_DBW_16;
		else
			mode = AT91_SMC_DBW_8;
		at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
	}

	if (cpu_is_at91sam9g20()) {
		/* Timing for sam9g20 */
		/* set the bus interface characteristics */
		at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0)
				| AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));

		at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4)
				| AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));

		at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));

		if (data->bus_width_16)
			mode = AT91_SMC_DBW_16;
		else
			mode = AT91_SMC_DBW_8;
		at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(3));
	}

	/* enable pin */
	if (data->enable_pin)
		at91_set_gpio_output(data->enable_pin, 1);

	/* ready/busy pin */
	if (data->rdy_pin)
		at91_set_gpio_input(data->rdy_pin, 1);

	/* card detect pin */
	if (data->det_pin)
		at91_set_gpio_input(data->det_pin, 1);

	nand_data = *data;
	platform_device_register(&at91sam9260_nand_device);
}