static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) { u32 status; disable_irq_nosync(irq); status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; if (status == 0) { spurious_interrupt(); goto enable; } if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { /* TODO: flush DDR? */ generic_handle_irq(ATH79_IP2_IRQ(0)); } if (status & QCA955X_EXT_INT_WMAC_ALL) { /* TODO: flush DDR? */ generic_handle_irq(ATH79_IP2_IRQ(1)); } enable: enable_irq(irq); }
static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) { u32 status; status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { ath79_ddr_wb_flush(3); generic_handle_irq(ATH79_IP2_IRQ(0)); } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { ath79_ddr_wb_flush(4); generic_handle_irq(ATH79_IP2_IRQ(1)); } else { spurious_interrupt(); } }
static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) { u32 status; disable_irq_nosync(irq); status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) { ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE); generic_handle_irq(ATH79_IP2_IRQ(0)); } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) { ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC); generic_handle_irq(ATH79_IP2_IRQ(1)); } else { spurious_interrupt(); } enable_irq(irq); }
static void qca955x_ip2_irq_dispatch(struct irq_desc *desc) { u32 status; status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS); status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL; if (status == 0) { spurious_interrupt(); return; } if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { /* TODO: flush DDR? */ generic_handle_irq(ATH79_IP2_IRQ(0)); } if (status & QCA955X_EXT_INT_WMAC_ALL) { /* TODO: flush DDR? */ generic_handle_irq(ATH79_IP2_IRQ(1)); } }
int __init ath79_register_pci(void) { if (soc_is_ar71xx()) return ar71xx_pcibios_init(); if (soc_is_ar724x()) return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); if (soc_is_ar9342() || soc_is_ar9344()) { u32 bootstrap; bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); } return -ENODEV; }