static void mt_auxadc_disable_penirq(void) { if(adc_rtp_set){ adc_rtp_set = 0; AUXADC_DRV_SetBits16((volatile u16 *)AUXADC_CON_RTP, 1); //Turn off PENIRQ detection circuit AUXADC_DRV_SetBits16((volatile u16 *)AUXADC_TP_CMD, 1); //run once touch function mt_tpd_read_adc(TP_CMD_ADDR_X); } }
void mt_auxadc_hal_resume(void) { pr_debug("******** MT auxadc driver resume!! ********\n" ); if(enable_clock(MT_PDN_PERI_AUXADC,"AUXADC")) printk("hwEnableClock AUXADC failed!!!."); AUXADC_DRV_SetBits16((volatile u16 *)AUXADC_CON_RTP, 1); //disable RTP }
void mt_auxadc_hal_resume(void) { AUXADC_DRV_SetBits16((volatile u16 *)AUXADC_CON_RTP, 1); //disable RTP }
void mt_auxadc_hal_init(void) { mt_auxadc_cal_prepare(); AUXADC_DRV_SetBits16((volatile u16 *)AUXADC_CON_RTP, 1); //disable RTP }
int IMM_auxadc_GetOneChannelValue(int dwChannel, int data[4], int* rawdata) { unsigned int channel[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; int idle_count =0; int data_ready_count=0; mutex_lock(&mutex_get_cali_value); #if 0 if(enable_clock(MT_PDN_PERI_AUXADC,"AUXADC")) { printk("hwEnableClock AUXADC failed."); } #endif if(dwChannel == PAD_AUX_XP)mt_auxadc_disable_penirq(); //step1 check con2 if auxadc is busy while ((*(volatile u16 *)AUXADC_CON2) & 0x01) { printk("[adc_api]: wait for module idle\n"); msleep(100); idle_count++; if(idle_count>30) { //wait for idle time out printk("[adc_api]: wait for auxadc idle time out\n"); mutex_unlock(&mutex_get_cali_value); return -1; } } // step2 clear bit if(0 == adc_auto_set) { //clear bit AUXADC_DRV_ClearBits16((volatile u16 *)AUXADC_CON1, (1 << dwChannel)); } //step3 read channle and make sure old ready bit ==0 while ((*(volatile u16 *)(AUXADC_DAT0 + dwChannel * 0x04)) & (1<<12)) { printk("[adc_api]: wait for channel[%d] ready bit clear\n",dwChannel); msleep(10); data_ready_count++; if(data_ready_count>30) { //wait for idle time out printk("[adc_api]: wait for channel[%d] ready bit clear time out\n",dwChannel); mutex_unlock(&mutex_get_cali_value); return -2; } } //step4 set bit to trigger sample if(0==adc_auto_set) { AUXADC_DRV_SetBits16((volatile u16 *)AUXADC_CON1, (1 << dwChannel)); } //step5 read channle and make sure ready bit ==1 udelay(25);//we must dealay here for hw sample cahnnel data while (0==((*(volatile u16 *)(AUXADC_DAT0 + dwChannel * 0x04)) & (1<<12))) { printk("[adc_api]: wait for channel[%d] ready bit ==1\n",dwChannel); msleep(10); data_ready_count++; if(data_ready_count>30) { //wait for idle time out printk("[adc_api]: wait for channel[%d] data ready time out\n",dwChannel); mutex_unlock(&mutex_get_cali_value); return -3; } } //step6 read data channel[dwChannel] = (*(volatile u16 *)(AUXADC_DAT0 + dwChannel * 0x04)) & 0x0FFF; if(NULL != rawdata) { *rawdata = channel[dwChannel]; } //printk("[adc_api: imm mode raw data => channel[%d] = %d\n",dwChannel, channel[dwChannel]); //printk("[adc_api]: imm mode => channel[%d] = %d.%02d\n", dwChannel, (channel[dwChannel] * 150 / AUXADC_PRECISE / 100), ((channel[dwChannel] * 150 / AUXADC_PRECISE) % 100)); data[0] = (channel[dwChannel] * 150 / AUXADC_PRECISE / 100); data[1] = ((channel[dwChannel] * 150 / AUXADC_PRECISE) % 100); #if 0 if(disable_clock(MT_PDN_PERI_AUXADC,"AUXADC")) { printk("hwEnableClock AUXADC failed."); } #endif mutex_unlock(&mutex_get_cali_value); return 0; }
static u16 mt_tpd_read_adc(u16 pos) { AUXADC_DRV_SetBits16((volatile u16 *)AUXADC_TP_ADDR, pos); AUXADC_DRV_SetBits16((volatile u16 *)AUXADC_TP_CON0, 0x01); while(0x01 & AUXADC_DRV_ReadReg16((volatile u16 *)AUXADC_TP_CON0)) { ; } //wait for write finish return AUXADC_DRV_ReadReg16((volatile u16 *)AUXADC_TP_DATA0); }