static int uninorth_create_gatt_table(void) { char *table; char *table_end; int size; int page_order; int num_entries; int i; void *temp; struct page *page; /* We can't handle 2 level gatt's */ if (agp_bridge->driver->size_type == LVL2_APER_SIZE) return -EINVAL; table = NULL; i = agp_bridge->aperture_size_idx; temp = agp_bridge->current_size; size = page_order = num_entries = 0; do { size = A_SIZE_32(temp)->size; page_order = A_SIZE_32(temp)->page_order; num_entries = A_SIZE_32(temp)->num_entries; table = (char *) __get_free_pages(GFP_KERNEL, page_order); if (table == NULL) { i++; agp_bridge->current_size = A_IDX32(agp_bridge); } else { agp_bridge->aperture_size_idx = i; } } while (!table && (i < agp_bridge->driver->num_aperture_sizes)); if (table == NULL) return -ENOMEM; table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) SetPageReserved(page); agp_bridge->gatt_table_real = (u32 *) table; agp_bridge->gatt_table = (u32 *)table; agp_bridge->gatt_bus_addr = virt_to_phys(table); for (i = 0; i < num_entries; i++) { agp_bridge->gatt_table[i] = (unsigned long) agp_bridge->scratch_page; } flush_dcache_range((unsigned long)table, (unsigned long)table_end); return 0; }
static int ali_configure(void) { u32 temp; struct aper_size_info_32 *current_size; current_size = A_SIZE_32(agp_bridge->current_size); /* aperture size and gatt addr */ pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000)) | (current_size->size_value & 0xf)); pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp); /* tlb control */ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010)); /* address to map to */ pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); temp &= 0xffffff7f; //enable TLB pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp); return 0; }
/* * Get the current Aperture size from the x86-64. * Note, that there may be multiple x86-64's, but we just return * the value from the first one we find. The set_size functions * keep the rest coherent anyway. Or at least should do. */ static int amd64_fetch_size(void) { struct pci_dev *dev; int i; u32 temp; struct aper_size_info_32 *values; dev = k8_northbridges[0]; if (dev==NULL) return 0; pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); temp = (temp & 0xe); values = A_SIZE_32(amd64_aperture_sizes); for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { if (temp == values[i].size_value) { agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); agp_bridge->aperture_size_idx = i; return values[i].size; } } return 0; }
static int uninorth_configure(void) { struct aper_size_info_32 *current_size; current_size = A_SIZE_32(agp_bridge->current_size); printk(KERN_INFO PFX "configuring for size idx: %d\n", current_size->size_value); /* aperture size and gatt addr */ pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_BASE, (agp_bridge->gatt_bus_addr & 0xfffff000) | current_size->size_value); /* HACK ALERT * UniNorth seem to be buggy enough not to handle properly when * the AGP aperture isn't mapped at bus physical address 0 */ agp_bridge->gart_bus_addr = 0; pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr); return 0; }
static int uninorth_free_gatt_table(void) { int page_order; char *table, *table_end; void *temp; struct page *page; temp = agp_bridge->current_size; page_order = A_SIZE_32(temp)->page_order; /* Do not worry about freeing memory, because if this is * called, then all agp memory is deallocated and removed * from the table. */ table = (char *) agp_bridge->gatt_table_real; table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) ClearPageReserved(page); free_pages((unsigned long) agp_bridge->gatt_table_real, page_order); return 0; }
static int uninorth_fetch_size(void) { int i; u32 temp; struct aper_size_info_32 *values; pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_BASE, &temp); temp &= ~(0xfffff000); values = A_SIZE_32(agp_bridge->driver->aperture_sizes); for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { if (temp == values[i].size_value) { agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); agp_bridge->aperture_size_idx = i; return values[i].size; } } agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); agp_bridge->aperture_size_idx = 1; return values[1].size; return 0; }
static void ali_cleanup(void) { struct aper_size_info_32 *previous_size; u32 temp; previous_size = A_SIZE_32(agp_bridge->previous_size); pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); // clear tag pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL, ((temp & 0xffffff00) | 0x00000001|0x00000002)); pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, ((temp & 0x00000ff0) | previous_size->size_value)); }
static void m1541_cache_flush(void) { int i, page_count; u32 temp; global_cache_flush(); page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order; for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) { pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp); pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, (((temp & ALI_CACHE_FLUSH_ADDR_MASK) | (agp_bridge->gatt_bus_addr + i)) | ALI_CACHE_FLUSH_EN)); } }
static int ali_configure(void) { u32 temp; struct aper_size_info_32 *current_size; current_size = A_SIZE_32(agp_bridge->current_size); /* aperture size and gatt addr */ pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp); temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000)) | (current_size->size_value & 0xf)); pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp); /* tlb control */ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp); pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010)); /* address to map to */ agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR); #if 0 if (agp_bridge->type == ALI_M1541) { u32 nlvm_addr = 0; switch (current_size->size_value) { case 0: break; case 1: nlvm_addr = 0x100000;break; case 2: nlvm_addr = 0x200000;break; case 3: nlvm_addr = 0x400000;break; case 4: nlvm_addr = 0x800000;break; case 6: nlvm_addr = 0x1000000;break; case 7: nlvm_addr = 0x2000000;break; case 8: nlvm_addr = 0x4000000;break; case 9: nlvm_addr = 0x8000000;break; case 10: nlvm_addr = 0x10000000;break; default: break; } nlvm_addr--; nlvm_addr&=0xfff00000; nlvm_addr+= agp_bridge->gart_bus_addr; nlvm_addr|=(agp_bridge->gart_bus_addr>>12); dev_info(&agp_bridge->dev->dev, "nlvm top &base = %8x\n", nlvm_addr); }
static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type) { int i, j, num_entries; void *temp; temp = agp_bridge->current_size; num_entries = A_SIZE_32(temp)->num_entries; if (type != 0 || mem->type != 0) /* We know nothing of memory types */ return -EINVAL; if ((pg_start + mem->page_count) > num_entries) return -EINVAL; j = pg_start; while (j < (pg_start + mem->page_count)) { if (!PGE_EMPTY(agp_bridge, agp_bridge->gatt_table[j])) return -EBUSY; j++; } for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { agp_bridge->gatt_table[j] = cpu_to_le32((mem->memory[i] & 0xfffff000) | 0x00000001UL); flush_dcache_range((unsigned long)__va(mem->memory[i]), (unsigned long)__va(mem->memory[i])+0x1000); } (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]); mb(); flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start], (unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]); uninorth_tlbflush(mem); return 0; }