/**Function************************************************************* Synopsis [Writes the logic network in the equation format.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Io_WriteEqn( Abc_Ntk_t * pNtk, char * pFileName ) { FILE * pFile; assert( Abc_NtkIsAigNetlist(pNtk) ); if ( Abc_NtkLatchNum(pNtk) > 0 ) printf( "Warning: only combinational portion is being written.\n" ); // check that the names are fine for the EQN format if ( !Io_NtkWriteEqnCheck(pNtk) ) return; // start the output stream pFile = fopen( pFileName, "w" ); if ( pFile == NULL ) { fprintf( stdout, "Io_WriteEqn(): Cannot open the output file \"%s\".\n", pFileName ); return; } fprintf( pFile, "# Equations for \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() ); // write the equations for the network Io_NtkWriteEqnOne( pFile, pNtk ); fprintf( pFile, "\n" ); fclose( pFile ); }
/**Function************************************************************* Synopsis [Write verilog.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName ) { Abc_Ntk_t * pNetlist; FILE * pFile; int i; // can only write nodes represented using local AIGs if ( !Abc_NtkIsAigNetlist(pNtk) && !Abc_NtkIsMappedNetlist(pNtk) ) { printf( "Io_WriteVerilog(): Can produce Verilog for mapped or AIG netlists only.\n" ); return; } // start the output stream pFile = fopen( pFileName, "w" ); if ( pFile == NULL ) { fprintf( stdout, "Io_WriteVerilog(): Cannot open the output file \"%s\".\n", pFileName ); return; } // write the equations for the network fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() ); fprintf( pFile, "\n" ); // write modules if ( pNtk->pDesign ) { // write the network first Io_WriteVerilogInt( pFile, pNtk ); // write other things Vec_PtrForEachEntry( Abc_Ntk_t *, pNtk->pDesign->vModules, pNetlist, i ) { assert( Abc_NtkIsNetlist(pNetlist) ); if ( pNetlist == pNtk ) continue; fprintf( pFile, "\n" ); Io_WriteVerilogInt( pFile, pNetlist ); } }