/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xFF000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x000FEEFFu);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00D80000u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000011u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00006D8Eu);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u);
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000060u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x000000EEu);
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000002u);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00000024u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00036C00u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0001u, /* Base address: 0x400F0000 Count: 1 */
0x400F3052u, /* Base address: 0x400F3000 Count: 82 */
0x400F3125u, /* Base address: 0x400F3100 Count: 37 */
0x400F3244u, /* Base address: 0x400F3200 Count: 68 */
0x400F3333u, /* Base address: 0x400F3300 Count: 51 */
0x400F4009u, /* Base address: 0x400F4000 Count: 9 */
0x400F410Du, /* Base address: 0x400F4100 Count: 13 */
0x400F4204u, /* Base address: 0x400F4200 Count: 4 */
0x400F430Eu, /* Base address: 0x400F4300 Count: 14 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x83u, 0x6Fu},
{0x04u, 0x0Cu},
{0x06u, 0x30u},
{0x08u, 0x28u},
{0x0Au, 0x14u},
{0x0Cu, 0x01u},
{0x14u, 0x14u},
{0x15u, 0x96u},
{0x16u, 0x28u},
{0x17u, 0x69u},
{0x19u, 0x0Fu},
{0x1Au, 0x03u},
{0x1Bu, 0xF0u},
{0x25u, 0x33u},
{0x27u, 0xCCu},
{0x28u, 0x0Cu},
{0x29u, 0x55u},
{0x2Au, 0x70u},
{0x2Bu, 0xAAu},
{0x30u, 0x02u},
{0x32u, 0x40u},
{0x33u, 0xFFu},
{0x34u, 0x3Cu},
{0x35u, 0xFFu},
{0x36u, 0x01u},
{0x3Eu, 0x40u},
{0x40u, 0x10u},
{0x41u, 0x02u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Du, 0xA0u},
{0x4Fu, 0x01u},
{0x50u, 0x18u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x62u, 0x80u},
{0x64u, 0x40u},
{0x65u, 0x40u},
{0x66u, 0x80u},
{0x68u, 0x40u},
{0x6Au, 0x80u},
{0x6Cu, 0x40u},
{0x6Du, 0x20u},
{0x6Eu, 0x80u},
{0x82u, 0x01u},
{0x86u, 0x02u},
{0x8Au, 0x04u},
{0x96u, 0x08u},
{0x9Au, 0x10u},
{0xA4u, 0x09u},
{0xA6u, 0x06u},
{0xACu, 0x05u},
{0xAEu, 0x0Au},
{0xB0u, 0x0Fu},
{0xB4u, 0x10u},
{0xBEu, 0x01u},
{0xC0u, 0x50u},
{0xC1u, 0x06u},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCDu, 0xAFu},
{0xCEu, 0x07u},
{0xCFu, 0x01u},
{0xD0u, 0x18u},
{0xD8u, 0x04u},
{0xDAu, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE2u, 0x80u},
{0xE4u, 0x40u},
{0xE5u, 0x40u},
{0xE6u, 0x80u},
{0xE8u, 0x40u},
{0xEAu, 0x80u},
{0xECu, 0x40u},
{0xEDu, 0x20u},
{0xEEu, 0x80u},
{0x00u, 0x48u},
{0x03u, 0x08u},
{0x05u, 0x2Au},
{0x09u, 0x20u},
{0x0Au, 0x10u},
{0x0Cu, 0x10u},
{0x0Du, 0x04u},
{0x12u, 0x08u},
{0x15u, 0x40u},
{0x17u, 0x04u},
{0x18u, 0x45u},
{0x19u, 0x04u},
{0x1Au, 0x1Au},
{0x1Bu, 0x20u},
{0x1Cu, 0x88u},
{0x1Du, 0x10u},
{0x21u, 0x28u},
{0x29u, 0x04u},
{0x2Bu, 0x08u},
{0x31u, 0x10u},
{0x32u, 0x08u},
{0x40u, 0x05u},
{0x4Eu, 0x05u},
{0x6Du, 0x40u},
{0x6Fu, 0x04u},
{0x81u, 0x08u},
{0x86u, 0x08u},
{0x89u, 0x04u},
{0xC0u, 0x77u},
{0xC2u, 0x66u},
{0xC4u, 0xA2u},
{0xCAu, 0x06u},
{0xCCu, 0x06u},
{0xD0u, 0x0Cu},
{0xD2u, 0x30u},
{0xE2u, 0x08u},
{0xE4u, 0x80u},
{0x39u, 0x02u},
{0x40u, 0x50u},
{0x41u, 0x06u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Du, 0xAFu},
{0x4Eu, 0x07u},
{0x4Fu, 0x01u},
{0x50u, 0x18u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Cu, 0x80u},
{0x5Fu, 0x21u},
{0x60u, 0x40u},
{0x62u, 0x80u},
{0x64u, 0x40u},
{0x65u, 0x40u},
{0x66u, 0x80u},
{0x68u, 0x40u},
{0x6Au, 0x80u},
{0x6Cu, 0x40u},
{0x6Du, 0x20u},
{0x6Eu, 0x80u},
{0x8Cu, 0x01u},
{0x8Fu, 0x03u},
{0x94u, 0x04u},
{0x95u, 0x01u},
{0xA2u, 0x0Cu},
{0xA6u, 0x03u},
{0xB0u, 0x02u},
{0xB2u, 0x08u},
{0xB3u, 0x02u},
{0xB4u, 0x04u},
{0xB6u, 0x01u},
{0xB7u, 0x01u},
{0xBEu, 0x50u},
{0xBFu, 0x40u},
{0xC0u, 0x10u},
{0xC1u, 0x02u},
{0xC5u, 0x35u},
{0xC6u, 0xC2u},
{0xC7u, 0x0Eu},
{0xC8u, 0x1Fu},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCDu, 0xAFu},
{0xCEu, 0x07u},
{0xCFu, 0x01u},
{0xD0u, 0x18u},
{0xD4u, 0x0Fu},
{0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDAu, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE2u, 0x80u},
{0xE4u, 0x40u},
{0xE5u, 0x40u},
{0xE6u, 0x80u},
{0xE8u, 0x40u},
{0xEAu, 0x80u},
{0xECu, 0x40u},
{0xEDu, 0x20u},
{0xEEu, 0x80u},
{0x00u, 0x40u},
{0x0Au, 0x10u},
{0x10u, 0xA0u},
{0x18u, 0x40u},
{0x19u, 0x40u},
{0x1Au, 0x14u},
{0x22u, 0x08u},
{0x23u, 0x02u},
{0x27u, 0x80u},
{0x32u, 0x08u},
{0x38u, 0x80u},
{0x40u, 0x01u},
{0x43u, 0x20u},
{0x48u, 0xA0u},
{0x4Eu, 0x05u},
{0x50u, 0x40u},
{0x51u, 0x08u},
{0x52u, 0x10u},
{0x59u, 0x40u},
{0x5Au, 0x04u},
{0x5Bu, 0x22u},
{0x61u, 0x08u},
{0x62u, 0x12u},
{0x7Eu, 0x20u},
{0x80u, 0x40u},
{0x81u, 0x28u},
{0x83u, 0x20u},
{0x84u, 0x40u},
{0x8Au, 0x02u},
{0x8Du, 0x02u},
{0x8Eu, 0x20u},
{0x8Fu, 0x80u},
{0x90u, 0x01u},
{0x92u, 0x0Au},
{0x9Du, 0x2Au},
{0xA0u, 0x40u},
{0xA3u, 0x20u},
{0xB0u, 0x10u},
{0xB3u, 0x08u},
{0xC0u, 0x01u},
{0xC2u, 0x04u},
{0xC4u, 0x0Cu},
{0xCCu, 0x02u},
{0xCEu, 0x08u},
{0xD0u, 0x0Cu},
{0xD2u, 0x30u},
{0xD6u, 0x0Fu},
{0xD8u, 0x07u},
{0xDEu, 0x40u},
{0xE0u, 0x40u},
{0xE6u, 0x20u},
{0x0Bu, 0x10u},
{0x5Fu, 0x20u},
{0x6Bu, 0x01u},
{0x83u, 0x20u},
{0x8Bu, 0x10u},
{0xC2u, 0x10u},
{0xD6u, 0x20u},
{0xDAu, 0x40u},
{0xE2u, 0x80u},
{0x03u, 0x88u},
{0x05u, 0x10u},
{0x4Au, 0x02u},
{0x81u, 0x10u},
{0x83u, 0x08u},
{0x86u, 0x02u},
{0x8Bu, 0x01u},
{0x8Fu, 0x80u},
{0x9Fu, 0x01u},
{0xC0u, 0xD0u},
{0xD2u, 0x10u},
{0xE2u, 0x40u},
{0xE4u, 0xA0u},
{0x0Bu, 0x80u},
{0x0Du, 0x01u},
{0x87u, 0x40u},
{0xC2u, 0x0Cu},
{0x09u, 0x01u},
{0x1Cu, 0x10u},
{0x30u, 0x08u},
{0x60u, 0x10u},
{0x8Cu, 0x08u},
{0x8Du, 0x01u},
{0xB1u, 0x01u},
{0xC2u, 0x08u},
{0xC6u, 0x04u},
{0xCCu, 0x02u},
{0xD8u, 0x02u},
{0xE2u, 0x08u},
{0xE4u, 0x08u},
{0xEAu, 0x04u},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000030u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x000000E0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0002EE00u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x0000000Eu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL7), 0x000000EEu);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x02000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x000C0000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x00A20000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x02000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG12), 0x00000200u);
/* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000EEE1Eu);
/* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x00000001u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000001u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT0_BASE), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00001DB6u);
/* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000082u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00000266u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000080u);
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x0000000Fu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00009000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x0000000Fu);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x00000031u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00032D86u);
/* IOPINS0_4 Starting address: CYDEV_GPIO_PRT4_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT4_BASE), 0x00000001u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_PC), 0x00000004u);
/* IOPINS0_5 Starting address: CYDEV_GPIO_PRT5_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT5_PC), 0x00030C00u);
/* IOPINS0_7 Starting address: CYDEV_GPIO_PRT7_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT7_BASE), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT7_PC), 0x00000024u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3241u, /* Base address: 0x400F3200 Count: 65 */
0x400F3326u, /* Base address: 0x400F3300 Count: 38 */
0x400F4105u, /* Base address: 0x400F4100 Count: 5 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4309u, /* Base address: 0x400F4300 Count: 9 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x01u, 0x04u},
{0x05u, 0x04u},
{0x07u, 0x08u},
{0x09u, 0x04u},
{0x0Bu, 0x08u},
{0x19u, 0x01u},
{0x1Bu, 0x02u},
{0x25u, 0x01u},
{0x29u, 0x01u},
{0x2Bu, 0x02u},
{0x2Eu, 0x01u},
{0x31u, 0x0Cu},
{0x35u, 0x03u},
{0x36u, 0x01u},
{0x39u, 0x22u},
{0x40u, 0x02u},
{0x45u, 0x01u},
{0x46u, 0x40u},
{0x47u, 0x05u},
{0x48u, 0x1Bu},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Cu, 0x02u},
{0x4Du, 0x20u},
{0x4Eu, 0xF0u},
{0x52u, 0x07u},
{0x58u, 0x04u},
{0x59u, 0x0Fu},
{0x5Au, 0x0Fu},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x62u, 0x48u},
{0x63u, 0xADu},
{0x64u, 0xC0u},
{0x66u, 0xC0u},
{0x8Fu, 0x01u},
{0xA4u, 0x01u},
{0xA8u, 0x01u},
{0xAAu, 0x02u},
{0xACu, 0x01u},
{0xAEu, 0x02u},
{0xB2u, 0x03u},
{0xB3u, 0x01u},
{0xB8u, 0x0Au},
{0xBEu, 0x01u},
{0xC0u, 0x04u},
{0xC7u, 0x10u},
{0xC8u, 0x21u},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCCu, 0x02u},
{0xCDu, 0x20u},
{0xCEu, 0xF0u},
{0xD2u, 0x03u},
{0xD8u, 0x0Eu},
{0xD9u, 0x04u},
{0xDAu, 0x0Eu},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0xE2u, 0x48u},
{0xE3u, 0xADu},
{0xE4u, 0xC0u},
{0xE6u, 0xC0u},
{0x10u, 0x2Au},
{0x15u, 0x40u},
{0x18u, 0x80u},
{0x1Au, 0x60u},
{0x1Fu, 0x80u},
{0x21u, 0x04u},
{0x24u, 0x40u},
{0x25u, 0x20u},
{0x2Fu, 0x28u},
{0x37u, 0x10u},
{0x39u, 0x80u},
{0x3Eu, 0x10u},
{0x3Fu, 0x0Au},
{0x42u, 0x40u},
{0x47u, 0x20u},
{0x48u, 0x20u},
{0x4Fu, 0x0Au},
{0x50u, 0x02u},
{0x57u, 0x28u},
{0x68u, 0x08u},
{0x69u, 0x80u},
{0x6Du, 0x40u},
{0x6Eu, 0x10u},
{0x6Fu, 0x10u},
{0x79u, 0x08u},
{0x7Fu, 0x80u},
{0x80u, 0x40u},
{0x82u, 0x10u},
{0x83u, 0x20u},
{0x89u, 0x20u},
{0x8Cu, 0x40u},
{0xC4u, 0x87u},
{0xCAu, 0x60u},
{0xCCu, 0x20u},
{0xCEu, 0xE8u},
{0xD0u, 0x21u},
{0xDEu, 0x82u},
{0xE4u, 0x04u},
{0x38u, 0x01u},
{0x3Cu, 0x01u},
{0x80u, 0x01u},
{0xCEu, 0xC0u},
{0xE2u, 0x80u},
{0x5Du, 0x08u},
{0xD6u, 0x01u},
{0x5Au, 0x01u},
{0x5Cu, 0x08u},
{0x80u, 0x08u},
{0x8Au, 0x01u},
{0x8Du, 0x08u},
{0x9Du, 0x08u},
{0xD6u, 0x03u},
{0xE0u, 0x02u},
{0xE4u, 0x01u},
{0x01u, 0x01u},
{0x10u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* PWR_BG_CONFIG Starting address: CYDEV_PWR_BG_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PWR_BG_CONFIG), 0x00040000u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x03000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x33000000u);
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00D80000u);
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_DR), 0x0000007Eu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00040000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x0000003Eu);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_DR), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00240000u);
/* IOPINS0_4 Starting address: CYDEV_GPIO_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_DR), 0x00000001u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_PC2), 0x00000001u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x10000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x40000000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0001u, /* Base address: 0x400F0000 Count: 1 */
0x400F3032u, /* Base address: 0x400F3000 Count: 50 */
0x400F3117u, /* Base address: 0x400F3100 Count: 23 */
0x400F3233u, /* Base address: 0x400F3200 Count: 51 */
0x400F331Au, /* Base address: 0x400F3300 Count: 26 */
0x400F4010u, /* Base address: 0x400F4000 Count: 16 */
0x400F410Cu, /* Base address: 0x400F4100 Count: 12 */
0x400F4208u, /* Base address: 0x400F4200 Count: 8 */
0x400F4308u, /* Base address: 0x400F4300 Count: 8 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x83u, 0x0Du},
{0x40u, 0x24u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Fu, 0x01u},
{0x50u, 0x18u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Du, 0x09u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x62u, 0x40u},
{0x64u, 0x40u},
{0x65u, 0x40u},
{0x66u, 0x80u},
{0x68u, 0x80u},
{0x6Au, 0x80u},
{0x6Cu, 0x80u},
{0x6Eu, 0x80u},
{0x82u, 0x02u},
{0x8Eu, 0x08u},
{0x98u, 0x02u},
{0x9Au, 0x04u},
{0x9Cu, 0x01u},
{0xB0u, 0x04u},
{0xB2u, 0x02u},
{0xB4u, 0x08u},
{0xB6u, 0x01u},
{0xBEu, 0x40u},
{0xC0u, 0x25u},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCDu, 0x83u},
{0xCEu, 0x03u},
{0xCFu, 0x01u},
{0xD0u, 0x18u},
{0xD8u, 0x04u},
{0xDAu, 0x04u},
{0xDDu, 0x09u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE2u, 0x40u},
{0xE4u, 0x40u},
{0xE5u, 0x40u},
{0xE6u, 0x80u},
{0xE8u, 0x80u},
{0xEAu, 0x80u},
{0xECu, 0x80u},
{0xEEu, 0x80u},
{0x05u, 0x01u},
{0x07u, 0x02u},
{0x0Eu, 0x04u},
{0x0Fu, 0x01u},
{0x1Du, 0x01u},
{0x1Eu, 0x04u},
{0x1Fu, 0x88u},
{0x41u, 0x01u},
{0x42u, 0x08u},
{0x46u, 0x08u},
{0x4Eu, 0x02u},
{0x69u, 0x80u},
{0x6Au, 0x20u},
{0x6Bu, 0x90u},
{0x70u, 0x90u},
{0x81u, 0x40u},
{0x83u, 0x18u},
{0x8Cu, 0x10u},
{0x8Eu, 0x10u},
{0xC0u, 0x90u},
{0xC2u, 0xC0u},
{0xD0u, 0x25u},
{0xD2u, 0x10u},
{0x40u, 0x24u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Du, 0x83u},
{0x4Eu, 0x03u},
{0x4Fu, 0x01u},
{0x50u, 0x18u},
{0x5Au, 0x04u},
{0x5Du, 0x09u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x62u, 0x40u},
{0x64u, 0x40u},
{0x65u, 0x40u},
{0x66u, 0x80u},
{0x68u, 0x80u},
{0x6Au, 0x80u},
{0x6Cu, 0x80u},
{0x6Eu, 0x80u},
{0x87u, 0x01u},
{0x93u, 0x01u},
{0xB7u, 0x01u},
{0xBFu, 0x40u},
{0xC0u, 0x24u},
{0xC5u, 0xECu},
{0xC7u, 0x20u},
{0xC8u, 0x23u},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCDu, 0x83u},
{0xCEu, 0x03u},
{0xCFu, 0x01u},
{0xD0u, 0x18u},
{0xD4u, 0x01u},
{0xD6u, 0x04u},
{0xD9u, 0x04u},
{0xDAu, 0x04u},
{0xDBu, 0x04u},
{0xDDu, 0x99u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE2u, 0x40u},
{0xE4u, 0x40u},
{0xE5u, 0x40u},
{0xE6u, 0x80u},
{0xE8u, 0x80u},
{0xEAu, 0x80u},
{0xECu, 0x80u},
{0xEEu, 0x80u},
{0x22u, 0x40u},
{0x31u, 0x02u},
{0x3Au, 0x08u},
{0x41u, 0x01u},
{0x42u, 0x08u},
{0x45u, 0x02u},
{0x46u, 0x08u},
{0x49u, 0x05u},
{0x51u, 0x03u},
{0x52u, 0x02u},
{0x59u, 0x05u},
{0x5Au, 0x80u},
{0x63u, 0x80u},
{0x83u, 0x40u},
{0x95u, 0x02u},
{0x9Au, 0x08u},
{0xA6u, 0x02u},
{0xABu, 0x83u},
{0xAEu, 0x08u},
{0xB3u, 0x80u},
{0xB4u, 0x80u},
{0xCCu, 0x01u},
{0xCEu, 0x02u},
{0xD0u, 0xA5u},
{0xD6u, 0x0Bu},
{0xD8u, 0x01u},
{0x03u, 0x08u},
{0x07u, 0x80u},
{0x0Eu, 0x02u},
{0x5Bu, 0x20u},
{0x6Cu, 0x80u},
{0x6Fu, 0x20u},
{0x73u, 0x02u},
{0x82u, 0x01u},
{0x83u, 0x22u},
{0xC0u, 0x60u},
{0xC2u, 0x80u},
{0xD4u, 0x80u},
{0xDAu, 0x80u},
{0xDCu, 0x60u},
{0xE2u, 0xA0u},
{0xE6u, 0x80u},
{0x56u, 0x01u},
{0x80u, 0x80u},
{0x9Au, 0x01u},
{0xA4u, 0x80u},
{0xAAu, 0x01u},
{0xABu, 0xA0u},
{0xAFu, 0x08u},
{0xD6u, 0x20u},
{0xE2u, 0x20u},
{0xE8u, 0x80u},
{0xECu, 0xC0u},
{0xEEu, 0x20u},
{0x5Bu, 0x01u},
{0x60u, 0x04u},
{0x8Cu, 0x04u},
{0x8Eu, 0x80u},
{0xD6u, 0x02u},
{0xD8u, 0x02u},
{0xE0u, 0x02u},
{0xE4u, 0x02u},
{0x5Fu, 0x08u},
{0x62u, 0x80u},
{0x9Bu, 0x08u},
{0xA2u, 0x80u},
{0xB3u, 0x01u},
{0xB7u, 0x08u},
{0xD6u, 0x03u},
{0xECu, 0x06u},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0330EE00u);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000083u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x0040004Eu);
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000019u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00000036u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000038u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000C1u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00D80000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC2), 0x00000001u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000060u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x001B0D80u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x80280000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00020000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00030000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x20000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x10000000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x0000000Du);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x0000000Eu);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3123u, /* Base address: 0x400F3100 Count: 35 */
0x400F3211u, /* Base address: 0x400F3200 Count: 17 */
0x400F3342u, /* Base address: 0x400F3300 Count: 66 */
0x400F4008u, /* Base address: 0x400F4000 Count: 8 */
0x400F4106u, /* Base address: 0x400F4100 Count: 6 */
0x400F420Bu, /* Base address: 0x400F4200 Count: 11 */
0x400F4312u, /* Base address: 0x400F4300 Count: 18 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x00u, 0x44u},
{0x03u, 0x08u},
{0x0Au, 0x15u},
{0x10u, 0x80u},
{0x12u, 0x29u},
{0x18u, 0x40u},
{0x1Au, 0x05u},
{0x1Bu, 0x28u},
{0x21u, 0x69u},
{0x22u, 0x80u},
{0x2Au, 0x12u},
{0x2Bu, 0x21u},
{0x30u, 0x80u},
{0x31u, 0x28u},
{0x32u, 0x01u},
{0x38u, 0x04u},
{0x39u, 0xA2u},
{0x40u, 0x04u},
{0x42u, 0x10u},
{0x4Au, 0x08u},
{0x52u, 0x10u},
{0x68u, 0x14u},
{0x6Bu, 0x01u},
{0x79u, 0x40u},
{0x87u, 0x08u},
{0x88u, 0x14u},
{0xC0u, 0x07u},
{0xC2u, 0x07u},
{0xC4u, 0x0Fu},
{0xCAu, 0x0Fu},
{0xCCu, 0x0Fu},
{0xCEu, 0x0Fu},
{0xD0u, 0x06u},
{0xD2u, 0x04u},
{0xDEu, 0x08u},
{0x40u, 0x23u},
{0x41u, 0x06u},
{0x47u, 0xB0u},
{0x48u, 0x20u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Fu, 0x40u},
{0x50u, 0x30u},
{0x5Au, 0x0Cu},
{0x5Du, 0x09u},
{0x5Fu, 0x01u},
{0x60u, 0xF0u},
{0x62u, 0x40u},
{0x63u, 0x02u},
{0x64u, 0x10u},
{0x65u, 0x12u},
{0x01u, 0x02u},
{0x03u, 0x20u},
{0x0Au, 0x59u},
{0x10u, 0x02u},
{0x12u, 0xA8u},
{0x18u, 0x24u},
{0x1Au, 0x79u},
{0x21u, 0x90u},
{0x22u, 0x29u},
{0x23u, 0x20u},
{0x29u, 0x02u},
{0x2Au, 0x10u},
{0x2Bu, 0x20u},
{0x31u, 0x80u},
{0x32u, 0x25u},
{0x38u, 0x22u},
{0x39u, 0x80u},
{0x3Eu, 0x30u},
{0x40u, 0x04u},
{0x42u, 0x10u},
{0x46u, 0x20u},
{0x47u, 0x20u},
{0x49u, 0x02u},
{0x4Au, 0x08u},
{0x4Eu, 0x04u},
{0x50u, 0x83u},
{0x56u, 0x01u},
{0x57u, 0x01u},
{0x69u, 0x40u},
{0x6Bu, 0x08u},
{0x79u, 0x40u},
{0x7Du, 0x40u},
{0x82u, 0x12u},
{0x83u, 0x08u},
{0x86u, 0x01u},
{0x89u, 0x80u},
{0x91u, 0x80u},
{0x94u, 0x04u},
{0x95u, 0x60u},
{0x96u, 0x52u},
{0x9Au, 0x10u},
{0x9Eu, 0x03u},
{0xA2u, 0x80u},
{0xA3u, 0x20u},
{0xA4u, 0x80u},
{0xA6u, 0x28u},
{0xA7u, 0x01u},
{0xADu, 0x01u},
{0xAEu, 0x01u},
{0xAFu, 0x01u},
{0xB1u, 0x28u},
{0xB4u, 0x40u},
{0xB6u, 0x40u},
{0xC0u, 0x0Cu},
{0xC2u, 0x0Fu},
{0xC4u, 0x0Fu},
{0xCAu, 0x07u},
{0xCCu, 0x0Fu},
{0xCEu, 0x0Du},
{0xD0u, 0x66u},
{0xD2u, 0x24u},
{0xDEu, 0x18u},
{0xE0u, 0x0Cu},
{0xE8u, 0x0Au},
{0xECu, 0x02u},
{0xEEu, 0xE0u},
{0x50u, 0x02u},
{0x5Fu, 0x02u},
{0x6Cu, 0x10u},
{0x87u, 0x02u},
{0xD4u, 0x80u},
{0xD6u, 0x80u},
{0xDAu, 0x80u},
{0xE6u, 0x40u},
{0x56u, 0x80u},
{0x9Au, 0x80u},
{0xB0u, 0x02u},
{0xB2u, 0x80u},
{0xB4u, 0x10u},
{0xD4u, 0x40u},
{0x52u, 0x40u},
{0x54u, 0x80u},
{0x58u, 0x14u},
{0x5Fu, 0x88u},
{0x66u, 0x02u},
{0x88u, 0x90u},
{0xD4u, 0x07u},
{0xD6u, 0x07u},
{0xD8u, 0x01u},
{0xE0u, 0x04u},
{0xE4u, 0x01u},
{0x5Au, 0x02u},
{0x5Cu, 0x04u},
{0x66u, 0x08u},
{0x80u, 0x04u},
{0x86u, 0x40u},
{0x8Au, 0x08u},
{0x92u, 0x02u},
{0x9Eu, 0x40u},
{0xACu, 0x04u},
{0xAEu, 0x01u},
{0xAFu, 0x80u},
{0xB6u, 0x02u},
{0xB7u, 0x08u},
{0xD6u, 0x03u},
{0xD8u, 0x01u},
{0xE0u, 0x04u},
{0xE8u, 0x02u},
{0xECu, 0x02u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
CYPACKED typedef struct {
void CYFAR *dest;
const void CYCODE *src;
uint16 size;
} CYPACKED_ATTR cfg_memcpy_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U1_BASE), 512u},
{(void CYFAR *)(CYDEV_UDB_P1_ROUTE_BASE), 256u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
/* UDB_0_1_0_CONFIG Address: CYDEV_UDB_P0_U0_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_0_1_0_CONFIG_VAL[] = {
0x00u, 0x04u, 0x00u, 0x08u, 0x7Eu, 0xFDu, 0x81u, 0x02u, 0x10u, 0x02u, 0x20u, 0x00u, 0x01u, 0x01u, 0x02u, 0x00u,
0x00u, 0xC3u, 0x00u, 0x3Cu, 0xCDu, 0x10u, 0x32u, 0x20u, 0x40u, 0x40u, 0x00u, 0x80u, 0x04u, 0x08u, 0x08u, 0x04u,
0x20u, 0x3Fu, 0x10u, 0xC0u, 0x80u, 0x02u, 0x00u, 0x00u, 0xF1u, 0x20u, 0x0Cu, 0x10u, 0x08u, 0x80u, 0x04u, 0x40u,
0x03u, 0x0Cu, 0x30u, 0x30u, 0xC0u, 0xC0u, 0x0Cu, 0x03u, 0x00u, 0x00u, 0xAAu, 0xAAu, 0x00u, 0x00u, 0x00u, 0x00u,
0x63u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0xB0u, 0x00u, 0x08u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x40u,
0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, 0x99u, 0x09u, 0x00u, 0x01u,
0xF0u, 0x00u, 0x40u, 0x02u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
/* UDB_0_0_0_CONFIG Address: CYDEV_UDB_P1_U1_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_0_0_0_CONFIG_VAL[] = {
0x04u, 0x00u, 0x41u, 0x02u, 0x45u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x33u, 0x00u, 0x08u, 0x00u, 0x00u,
0x01u, 0xF1u, 0x02u, 0x04u, 0x4Du, 0x30u, 0xB2u, 0x4Cu, 0xBAu, 0x88u, 0x45u, 0x00u, 0x40u, 0x10u, 0x80u, 0x20u,
0x45u, 0x00u, 0x00u, 0x08u, 0x45u, 0x08u, 0x00u, 0x00u, 0x55u, 0x20u, 0x8Au, 0x10u, 0x22u, 0x00u, 0x00u, 0x00u,
0x03u, 0x0Fu, 0x3Cu, 0x0Fu, 0x08u, 0xC0u, 0xC0u, 0x30u, 0x08u, 0x00u, 0x82u, 0xA0u, 0x00u, 0x00u, 0x00u, 0x00u,
0x63u, 0x02u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x0Bu, 0xF0u, 0x26u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x40u,
0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, 0x99u, 0x09u, 0x00u, 0x01u,
0xF0u, 0x00u, 0x40u, 0x02u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), BS_UDB_0_1_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYDEV_UDB_P1_U1_BASE), BS_UDB_0_0_0_CONFIG_VAL, 128u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
/* Copy device configuration data into registers */
for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
{
const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
void * CYDATA destPtr = mc->dest;
const void CYCODE * CYDATA srcPtr = mc->src;
uint16 CYDATA numBytes = mc->size;
CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x30000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33033333u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x3330EE00u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000081u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00C00006u);
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000001u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00000006u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000DFu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00D86DB6u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x000000E0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00DB0D80u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x40020000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00010000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x311B0000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0xD0000000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000001u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u);
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u);
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0003u, /* Base address: 0x400F0000 Count: 3 */
0x400F3069u, /* Base address: 0x400F3000 Count: 105 */
0x400F313Bu, /* Base address: 0x400F3100 Count: 59 */
0x400F3214u, /* Base address: 0x400F3200 Count: 20 */
0x400F3350u, /* Base address: 0x400F3300 Count: 80 */
0x400F4111u, /* Base address: 0x400F4100 Count: 17 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4301u, /* Base address: 0x400F4300 Count: 1 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x80u, 0x0Fu},
{0x82u, 0x38u},
{0x83u, 0x72u},
{0x00u, 0x80u},
{0x01u, 0x02u},
{0x02u, 0x20u},
{0x03u, 0x09u},
{0x04u, 0x20u},
{0x06u, 0xC0u},
{0x09u, 0x13u},
{0x0Au, 0x15u},
{0x0Cu, 0x40u},
{0x0Du, 0x10u},
{0x0Eu, 0x20u},
{0x10u, 0x13u},
{0x12u, 0x0Cu},
{0x14u, 0x13u},
{0x16u, 0x04u},
{0x18u, 0x03u},
{0x19u, 0x13u},
{0x1Au, 0x14u},
{0x20u, 0xE0u},
{0x24u, 0x0Au},
{0x26u, 0x14u},
{0x27u, 0x04u},
{0x28u, 0xE0u},
{0x2Du, 0x01u},
{0x2Eu, 0x08u},
{0x2Fu, 0x0Au},
{0x30u, 0x10u},
{0x31u, 0x03u},
{0x32u, 0xE0u},
{0x33u, 0x10u},
{0x34u, 0x0Fu},
{0x37u, 0x0Cu},
{0x3Au, 0x20u},
{0x3Eu, 0x01u},
{0x3Fu, 0x40u},
{0x40u, 0x23u},
{0x41u, 0x06u},
{0x45u, 0xECu},
{0x47u, 0x0Bu},
{0x48u, 0x13u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Eu, 0xF0u},
{0x4Fu, 0x44u},
{0x50u, 0x0Cu},
{0x54u, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x66u, 0xC0u},
{0x6Au, 0x40u},
{0x6Bu, 0x02u},
{0x80u, 0x10u},
{0x82u, 0x40u},
{0x84u, 0x0Cu},
{0x85u, 0x2Cu},
{0x86u, 0x71u},
{0x87u, 0x43u},
{0x88u, 0x10u},
{0x8Au, 0xACu},
{0x8Cu, 0x09u},
{0x8Eu, 0xD0u},
{0x93u, 0x0Cu},
{0x96u, 0x20u},
{0x99u, 0x71u},
{0x9Bu, 0x06u},
{0x9Eu, 0x03u},
{0xA3u, 0x08u},
{0xA4u, 0x14u},
{0xA5u, 0x71u},
{0xA7u, 0x0Eu},
{0xA8u, 0xDCu},
{0xA9u, 0x80u},
{0xAAu, 0x22u},
{0xABu, 0x13u},
{0xB3u, 0x0Fu},
{0xB4u, 0xE0u},
{0xB5u, 0x30u},
{0xB6u, 0x1Fu},
{0xB7u, 0xC0u},
{0xB9u, 0xA0u},
{0xBAu, 0x20u},
{0xBBu, 0x08u},
{0xBFu, 0x10u},
{0xC0u, 0x03u},
{0xC5u, 0x40u},
{0xC9u, 0xFFu},
{0xCAu, 0x07u},
{0xCBu, 0xFFu},
{0xCCu, 0x40u},
{0xCDu, 0x20u},
{0xCEu, 0xF0u},
{0xCFu, 0x05u},
{0xD0u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDAu, 0x04u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE1u, 0xA8u},
{0xE2u, 0x40u},
{0xE3u, 0x20u},
{0x00u, 0xA0u},
{0x01u, 0x09u},
{0x04u, 0x04u},
{0x05u, 0x22u},
{0x07u, 0x01u},
{0x08u, 0x10u},
{0x0Au, 0x80u},
{0x0Bu, 0x28u},
{0x0Du, 0xC0u},
{0x0Fu, 0x20u},
{0x10u, 0x81u},
{0x11u, 0x18u},
{0x15u, 0x08u},
{0x17u, 0x20u},
{0x19u, 0x28u},
{0x1Au, 0x44u},
{0x1Cu, 0x04u},
{0x1Du, 0x80u},
{0x1Fu, 0x30u},
{0x20u, 0x12u},
{0x21u, 0x01u},
{0x22u, 0x02u},
{0x25u, 0x04u},
{0x27u, 0x29u},
{0x29u, 0x08u},
{0x2Au, 0x80u},
{0x2Du, 0x02u},
{0x2Eu, 0x20u},
{0x2Fu, 0x20u},
{0x33u, 0x10u},
{0x34u, 0x01u},
{0x35u, 0x20u},
{0x37u, 0x01u},
{0x39u, 0x53u},
{0x3Du, 0x08u},
{0x42u, 0x24u},
{0x47u, 0x08u},
{0x49u, 0x01u},
{0x4Bu, 0x29u},
{0x4Du, 0x02u},
{0x51u, 0x04u},
{0x54u, 0x10u},
{0x56u, 0x20u},
{0x57u, 0x10u},
{0x58u, 0x10u},
{0x59u, 0x01u},
{0x5Au, 0x40u},
{0x5Bu, 0x04u},
{0x89u, 0x08u},
{0x8Au, 0x02u},
{0xC0u, 0xFFu},
{0xC2u, 0xAEu},
{0xC4u, 0x6Fu},
{0xCAu, 0xEAu},
{0xCCu, 0xA4u},
{0xCEu, 0x4Du},
{0xD0u, 0x46u},
{0xD2u, 0x04u},
{0xD6u, 0x0Fu},
{0x01u, 0x01u},
{0x02u, 0x04u},
{0x0Eu, 0x02u},
{0x12u, 0x02u},
{0x1Au, 0x01u},
{0x1Eu, 0x01u},
{0x2Cu, 0x08u},
{0x30u, 0x01u},
{0x32u, 0x02u},
{0x34u, 0x04u},
{0x35u, 0x01u},
{0x36u, 0x08u},
{0x3Eu, 0x45u},
{0x3Fu, 0x10u},
{0x54u, 0x18u},
{0x56u, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x00u, 0x80u},
{0x01u, 0x08u},
{0x03u, 0x48u},
{0x06u, 0x80u},
{0x07u, 0x02u},
{0x09u, 0x80u},
{0x0Au, 0x26u},
{0x0Bu, 0x40u},
{0x0Du, 0x11u},
{0x0Eu, 0x01u},
{0x12u, 0x03u},
{0x13u, 0x28u},
{0x15u, 0x80u},
{0x19u, 0x01u},
{0x1Au, 0x0Du},
{0x1Bu, 0x08u},
{0x1Cu, 0x04u},
{0x1Fu, 0x85u},
{0x20u, 0x08u},
{0x22u, 0x18u},
{0x23u, 0x42u},
{0x27u, 0x04u},
{0x2Au, 0x89u},
{0x2Bu, 0x08u},
{0x31u, 0x10u},
{0x32u, 0x05u},
{0x33u, 0x40u},
{0x38u, 0x04u},
{0x3Au, 0x22u},
{0x3Bu, 0x40u},
{0x3Cu, 0x08u},
{0x3Eu, 0x08u},
{0x3Fu, 0x01u},
{0x40u, 0x10u},
{0x42u, 0x05u},
{0x48u, 0x05u},
{0x51u, 0x11u},
{0x59u, 0x01u},
{0x5Du, 0x01u},
{0x64u, 0x80u},
{0x67u, 0x0Au},
{0x69u, 0x50u},
{0x6Bu, 0x10u},
{0x71u, 0x90u},
{0x72u, 0x20u},
{0x73u, 0x28u},
{0x80u, 0x80u},
{0x83u, 0x80u},
{0x84u, 0x40u},
{0x86u, 0x80u},
{0x89u, 0x01u},
{0x8Au, 0x08u},
{0x8Cu, 0x10u},
{0x8Fu, 0x40u},
{0x90u, 0x10u},
{0x91u, 0x80u},
{0x93u, 0x01u},
{0x95u, 0x50u},
{0x99u, 0x08u},
{0x9Au, 0x02u},
{0x9Eu, 0x80u},
{0x9Fu, 0x14u},
{0xA0u, 0x01u},
{0xA2u, 0x02u},
{0xA4u, 0x40u},
{0xA9u, 0x20u},
{0xAAu, 0x40u},
{0xB4u, 0x80u},
{0xB7u, 0x10u},
{0xC0u, 0x9Fu},
{0xC2u, 0xDFu},
{0xC4u, 0x87u},
{0xCAu, 0x0Fu},
{0xCCu, 0x0Fu},
{0xCEu, 0x8Fu},
{0xD0u, 0x0Eu},
{0xD2u, 0x0Cu},
{0xD6u, 0x81u},
{0xD8u, 0xB0u},
{0xEEu, 0x08u},
{0x03u, 0x80u},
{0x0Bu, 0x04u},
{0x67u, 0x02u},
{0x6Bu, 0x40u},
{0x6Fu, 0xA0u},
{0x83u, 0x41u},
{0x87u, 0x04u},
{0xA3u, 0x20u},
{0xAFu, 0x20u},
{0xC0u, 0x10u},
{0xC2u, 0x40u},
{0xD6u, 0x80u},
{0xDAu, 0x80u},
{0xDCu, 0x60u},
{0xE0u, 0x40u},
{0xE6u, 0xA0u},
{0xEEu, 0x10u},
{0x0Fu, 0x02u},
{0xC2u, 0x01u},
{0xAFu, 0x01u},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
CYPACKED typedef struct {
void CYFAR *dest;
const void CYCODE *src;
uint16 size;
} CYPACKED_ATTR cfg_memcpy_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 640u},
{(void CYFAR *)(CYDEV_UDB_P1_ROUTE_BASE), 256u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
/* UDB_0_0_0_CONFIG Address: CYDEV_UDB_P1_U1_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_0_0_0_CONFIG_VAL[] = {
0x00u, 0x60u, 0x33u, 0x00u, 0x03u, 0x00u, 0x00u, 0x04u, 0x4Fu, 0x18u, 0x30u, 0x00u, 0x01u, 0x1Cu, 0x00u, 0xE2u,
0x5Cu, 0x10u, 0x23u, 0x00u, 0x7Fu, 0xE7u, 0x00u, 0x18u, 0x73u, 0x08u, 0x0Cu, 0x00u, 0x08u, 0x00u, 0x00u, 0x63u,
0x00u, 0x40u, 0x00u, 0x00u, 0x04u, 0xFFu, 0x00u, 0x00u, 0x0Cu, 0x1Cu, 0x00u, 0xE1u, 0x02u, 0x24u, 0x00u, 0x00u,
0x40u, 0x1Fu, 0x2Cu, 0x60u, 0x0Fu, 0x00u, 0x1Cu, 0x80u, 0x00u, 0x80u, 0x28u, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u,
0x23u, 0x06u, 0x01u, 0x00u, 0x05u, 0x00u, 0xC0u, 0xE0u, 0x28u, 0xFFu, 0xFFu, 0xFFu, 0x62u, 0xA0u, 0xF0u, 0x41u,
0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x13u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x02u, 0x00u, 0x10u, 0x30u, 0x10u, 0x00u, 0x10u, 0x10u, 0x12u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
{(void CYFAR *)(CYDEV_UDB_P1_U1_BASE), BS_UDB_0_0_0_CONFIG_VAL, 128u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
/* Copy device configuration data into registers */
for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
{
const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
void * CYDATA destPtr = mc->dest;
const void CYCODE * CYDATA srcPtr = mc->src;
uint16 CYDATA numBytes = mc->size;
CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00300000u);
/* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL0), 0x00000000u);
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_PC */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00000000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x20000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x04000000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x0000000Eu);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x0000000Eu);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00070003u);
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00480000u);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00480000u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
static void ClockInit(void)
{
uint32_t status;
/* Enable all source clocks */
status = Cy_SysClk_WcoEnable(500000u);
if (CY_RET_SUCCESS != status) {
CyClockStartupError(CYCLOCKSTART_WCO_ERROR);
}
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
#if FEATURE_BLE
{
cy_stc_ble_bless_eco_cfg_params_t bleCfg = {
.ecoXtalStartUpTime = (785 / 31.25),
.loadCap = ((9.9 - 7.5) / 0.075),
.ecoFreq = CY_BLE_BLESS_ECO_FREQ_32MHZ,
.ecoSysDiv = CY_BLE_SYS_ECO_CLK_DIV_4
};
Cy_BLE_EcoStart(&bleCfg);
}
#endif // FEATURE_BLE
/* Configure CPU clock dividers */
Cy_SysClk_ClkFastSetDivider(0u);
Cy_SysClk_ClkPeriSetDivider((CY_CLK_HFCLK0_FREQ_HZ / CY_CLK_PERICLK_FREQ_HZ) - 1);
Cy_SysClk_ClkSlowSetDivider((CY_CLK_PERICLK_FREQ_HZ / CY_CLK_SYSTEM_FREQ_HZ) - 1);
/* Configure LF & HF clocks */
Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH1);
Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(0u);
/* Configure Path Clocks */
/* PLL path is used to clock HF domain from BLE ECO */
Cy_SysClk_ClkPathSetSource(2, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkPathSetSource(3, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkPathSetSource(4, CY_SYSCLK_CLKPATH_IN_IMO);
#if FEATURE_BLE
Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_ALTHF);
Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_ALTHF);
{
const cy_stc_pll_config_t pllConfig = {
.inputFreq = CY_CLK_ALTHF_FREQ_HZ,
.outputFreq = CY_CLK_HFCLK0_FREQ_HZ,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO
};
#else
Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkPathSetSource(1, CY_SYSCLK_CLKPATH_IN_IMO);
{
const cy_stc_pll_config_t pllConfig = {
.inputFreq = CY_CLK_IMO_FREQ_HZ,
.outputFreq = CY_CLK_HFCLK0_FREQ_HZ,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO
};
#endif // FEATURE_BLE
status = Cy_SysClk_PllConfigure(1u, &pllConfig);
if (CY_SYSCLK_SUCCESS != status) {
CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
}
}
status = Cy_SysClk_PllEnable(1u, 10000u);
if (CY_SYSCLK_SUCCESS != status) {
CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
}
/* Configure miscellaneous clocks */
Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV);
Cy_SysClk_ClkTimerSetDivider(0);
Cy_SysClk_ClkTimerEnable();
Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH0);
Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_DIV_4);
Cy_SysClk_ClkPumpEnable();
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
/* Disable unused clocks started by default */
Cy_SysClk_IloDisable();
/* Set memory wait states based on HFClk[0] */
Cy_SysLib_SetWaitStates(false, (CY_CLK_HFCLK0_FREQ_HZ + 990000) / 1000000UL);
}
/* Analog API Functions */
/*******************************************************************************
* Function Name: AnalogSetDefault
********************************************************************************
*
* Summary:
* Sets up the analog portions of the chip to default values based on chip
* configuration options from the project.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
static void AnalogSetDefault(void)
{
const cy_stc_sysanalog_config_t config = {
.startup = CY_SYSANALOG_STARTUP_NORMAL,
.iztat = CY_SYSANALOG_IZTAT_SOURCE_LOCAL,
.vref = CY_SYSANALOG_VREF_SOURCE_LOCAL_1_2V,
.deepSleep = CY_SYSANALOG_DEEPSLEEP_IPTAT_1
};
Cy_SysAnalog_Init(&config);
Cy_SysAnalog_Enable();
}
/*******************************************************************************
* Function Name: Cy_SystemInit
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
void Cy_SystemInit(void)
{
/* Set worst case memory wait states (150 MHz), ClockInit() will update */
Cy_SysLib_SetWaitStates(false, 150);
if(0u == Cy_SysLib_GetResetReason()) { /* POR, XRES, or BOD */
Cy_SysLib_ResetBackupDomain();
}
/* Power Mode */
Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_1_1V);
/* PMIC Control */
Cy_SysPm_UnlockPmic();
Cy_SysPm_DisablePmicOutput();
/* Pin0_0 and Pin0_1 drive WCO, configure as analog before configuring clock */
cy_reserve_io_pin(P0_0);
cy_reserve_io_pin(P0_1);
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0, CY_GPIO_DM_ANALOG, 0, P0_0_GPIO);
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1, CY_GPIO_DM_ANALOG, 0, P0_1_GPIO);
/* Clock */
ClockInit();
/******* Pre-defined port configuration section ********/
{
/* RGB LED is P_0_3 (R), P_1_1 (G) and P_11_1 (B) */
const uint32_t led_off = 1;
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 3, CY_GPIO_DM_STRONG_IN_OFF, led_off, P0_3_GPIO);
Cy_GPIO_Pin_FastInit(GPIO_PRT1, 1, CY_GPIO_DM_STRONG_IN_OFF, led_off, P1_1_GPIO);
Cy_GPIO_Pin_FastInit(GPIO_PRT11, 1, CY_GPIO_DM_STRONG_IN_OFF, led_off, P11_1_GPIO);
/* USER BUTTON is P_0_4 */
Cy_GPIO_Pin_FastInit(GPIO_PRT0, 4, CY_GPIO_DM_PULLUP, 1, P0_4_GPIO);
/* Configure hw debug interface on port 6 */
cy_reserve_io_pin(P6_6);
cy_reserve_io_pin(P6_7);
Cy_GPIO_Pin_FastInit(GPIO_PRT6, 6, CY_GPIO_DM_PULLUP, 0, P6_6_CPUSS_SWJ_SWDIO_TMS);
Cy_GPIO_Pin_FastInit(GPIO_PRT6, 7, CY_GPIO_DM_PULLDOWN, 0, P6_7_CPUSS_SWJ_SWCLK_TCLK);
}
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0001u, /* Base address: 0x400F0000 Count: 1 */
0x400F3028u, /* Base address: 0x400F3000 Count: 40 */
0x400F3108u, /* Base address: 0x400F3100 Count: 8 */
0x400F321Fu, /* Base address: 0x400F3200 Count: 31 */
0x400F3315u, /* Base address: 0x400F3300 Count: 21 */
0x400F4004u, /* Base address: 0x400F4000 Count: 4 */
0x400F4105u, /* Base address: 0x400F4100 Count: 5 */
0x400F4304u, /* Base address: 0x400F4300 Count: 4 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x82u, 0x0Du},
{0x40u, 0x51u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Fu, 0x01u},
{0x50u, 0x18u},
{0x5Au, 0x04u},
{0x5Du, 0x09u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x62u, 0x40u},
{0x64u, 0x40u},
{0x65u, 0x40u},
{0x66u, 0x80u},
{0x68u, 0x80u},
{0x6Au, 0x80u},
{0x6Cu, 0x80u},
{0x6Eu, 0x80u},
{0xC0u, 0x41u},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCDu, 0x83u},
{0xCEu, 0x03u},
{0xCFu, 0x01u},
{0xD0u, 0x18u},
{0xD2u, 0x80u},
{0xDAu, 0x04u},
{0xDBu, 0x04u},
{0xDDu, 0x99u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE2u, 0x40u},
{0xE4u, 0x40u},
{0xE5u, 0x40u},
{0xE6u, 0x80u},
{0xE8u, 0x80u},
{0xEAu, 0x80u},
{0xECu, 0x80u},
{0xEEu, 0x80u},
{0x42u, 0x02u},
{0x46u, 0x82u},
{0x48u, 0x01u},
{0x74u, 0x01u},
{0x76u, 0x80u},
{0x77u, 0x80u},
{0xD0u, 0x98u},
{0xD2u, 0x08u},
{0x0Eu, 0x01u},
{0x2Eu, 0x01u},
{0x30u, 0x01u},
{0x3Eu, 0x01u},
{0x40u, 0x41u},
{0x45u, 0xECu},
{0x47u, 0x20u},
{0x48u, 0x23u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Du, 0x83u},
{0x4Eu, 0x03u},
{0x4Fu, 0x01u},
{0x50u, 0x18u},
{0x54u, 0x01u},
{0x56u, 0x04u},
{0x58u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Du, 0x99u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x62u, 0x40u},
{0x64u, 0x40u},
{0x65u, 0x40u},
{0x66u, 0x80u},
{0x68u, 0x80u},
{0x6Au, 0x80u},
{0x6Cu, 0x80u},
{0x6Eu, 0x80u},
{0x06u, 0x02u},
{0x17u, 0x80u},
{0x1Eu, 0x80u},
{0x46u, 0x82u},
{0x4Du, 0x04u},
{0x4Fu, 0x01u},
{0x56u, 0x02u},
{0x5Du, 0x04u},
{0x5Eu, 0x80u},
{0x5Fu, 0x01u},
{0x67u, 0x80u},
{0x87u, 0x40u},
{0x9Au, 0x80u},
{0x9Bu, 0x80u},
{0x9Eu, 0x02u},
{0xC0u, 0x80u},
{0xC4u, 0x80u},
{0xD0u, 0x90u},
{0xD6u, 0xD0u},
{0xD8u, 0x80u},
{0xE2u, 0x80u},
{0x53u, 0x04u},
{0x6Fu, 0x02u},
{0xD4u, 0x20u},
{0xDAu, 0x80u},
{0x87u, 0x02u},
{0x8Bu, 0x04u},
{0x97u, 0x08u},
{0xA7u, 0x02u},
{0xE2u, 0x10u},
{0x19u, 0x08u},
{0x89u, 0x08u},
{0xC6u, 0x08u},
{0xE2u, 0x01u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00993000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000001u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000028u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00031C00u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x00000020u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3030u, /* Base address: 0x400F3000 Count: 48 */
0x400F3126u, /* Base address: 0x400F3100 Count: 38 */
0x400F3244u, /* Base address: 0x400F3200 Count: 68 */
0x400F333Au, /* Base address: 0x400F3300 Count: 58 */
0x400F4006u, /* Base address: 0x400F4000 Count: 6 */
0x400F410Du, /* Base address: 0x400F4100 Count: 13 */
0x400F4208u, /* Base address: 0x400F4200 Count: 8 */
0x400F431Fu, /* Base address: 0x400F4300 Count: 31 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x12u, 0x01u},
{0x13u, 0x01u},
{0x22u, 0x02u},
{0x2Cu, 0x01u},
{0x2Fu, 0x01u},
{0x30u, 0x02u},
{0x33u, 0x01u},
{0x34u, 0x01u},
{0x3Eu, 0x10u},
{0x3Fu, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x80u, 0x08u},
{0x84u, 0x02u},
{0x86u, 0x04u},
{0x88u, 0x04u},
{0x8Au, 0x02u},
{0x8Bu, 0x01u},
{0x8Cu, 0x04u},
{0x8Eu, 0x02u},
{0x8Fu, 0x04u},
{0x90u, 0x04u},
{0x92u, 0x02u},
{0x97u, 0x02u},
{0x98u, 0x04u},
{0x9Au, 0x02u},
{0x9Bu, 0x04u},
{0x9Cu, 0x04u},
{0x9Eu, 0x02u},
{0xA2u, 0x01u},
{0xA3u, 0x08u},
{0xAAu, 0x08u},
{0xB0u, 0x08u},
{0xB1u, 0x04u},
{0xB2u, 0x01u},
{0xB3u, 0x08u},
{0xB4u, 0x06u},
{0xB5u, 0x01u},
{0xB7u, 0x02u},
{0xBAu, 0x20u},
{0xBEu, 0x01u},
{0xBFu, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0x04u, 0x06u},
{0x05u, 0x20u},
{0x07u, 0x01u},
{0x08u, 0x02u},
{0x0Eu, 0x08u},
{0x0Fu, 0x82u},
{0x10u, 0x02u},
{0x11u, 0x02u},
{0x17u, 0x22u},
{0x18u, 0x08u},
{0x19u, 0x02u},
{0x1Bu, 0x01u},
{0x1Cu, 0x04u},
{0x1Eu, 0x50u},
{0x20u, 0x10u},
{0x26u, 0x04u},
{0x27u, 0x45u},
{0x28u, 0x02u},
{0x2Du, 0x02u},
{0x30u, 0x02u},
{0x36u, 0x04u},
{0x37u, 0x20u},
{0x3Du, 0x40u},
{0x3Eu, 0x10u},
{0x68u, 0x02u},
{0x6Cu, 0x01u},
{0x6Du, 0x40u},
{0x80u, 0x10u},
{0x82u, 0x40u},
{0x8Fu, 0x20u},
{0xC0u, 0xF0u},
{0xC2u, 0xD8u},
{0xC4u, 0x59u},
{0xCAu, 0x88u},
{0xCCu, 0x61u},
{0xCEu, 0x30u},
{0xE0u, 0x04u},
{0xE4u, 0x01u},
{0x00u, 0x04u},
{0x02u, 0x08u},
{0x08u, 0x04u},
{0x09u, 0x02u},
{0x0Au, 0x08u},
{0x0Bu, 0x05u},
{0x0Cu, 0x08u},
{0x0Eu, 0x04u},
{0x0Fu, 0x10u},
{0x13u, 0x08u},
{0x14u, 0x04u},
{0x15u, 0x01u},
{0x16u, 0x08u},
{0x17u, 0x02u},
{0x19u, 0x02u},
{0x1Au, 0x10u},
{0x1Bu, 0x01u},
{0x1Eu, 0x02u},
{0x20u, 0x04u},
{0x22u, 0x08u},
{0x25u, 0x02u},
{0x27u, 0x01u},
{0x28u, 0x04u},
{0x29u, 0x02u},
{0x2Au, 0x09u},
{0x2Bu, 0x01u},
{0x2Du, 0x02u},
{0x2Fu, 0x01u},
{0x30u, 0x01u},
{0x31u, 0x10u},
{0x32u, 0x10u},
{0x33u, 0x04u},
{0x34u, 0x02u},
{0x35u, 0x03u},
{0x36u, 0x0Cu},
{0x37u, 0x08u},
{0x3Au, 0x80u},
{0x3Bu, 0x20u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Fu, 0x01u},
{0x80u, 0x01u},
{0x82u, 0x02u},
{0x84u, 0x02u},
{0x86u, 0x01u},
{0x88u, 0x01u},
{0x8Au, 0x0Au},
{0x8Fu, 0x01u},
{0x96u, 0x04u},
{0x9Cu, 0x01u},
{0x9Eu, 0x12u},
{0xA3u, 0x04u},
{0xA8u, 0x01u},
{0xAAu, 0x02u},
{0xACu, 0x01u},
{0xAEu, 0x02u},
{0xB0u, 0x08u},
{0xB1u, 0x02u},
{0xB2u, 0x10u},
{0xB3u, 0x04u},
{0xB4u, 0x03u},
{0xB6u, 0x04u},
{0xB7u, 0x01u},
{0xBAu, 0x20u},
{0xBFu, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDFu, 0x01u},
{0x01u, 0x02u},
{0x03u, 0x28u},
{0x05u, 0x41u},
{0x07u, 0x04u},
{0x09u, 0x88u},
{0x0Eu, 0x19u},
{0x11u, 0x40u},
{0x13u, 0x10u},
{0x16u, 0x08u},
{0x17u, 0x02u},
{0x19u, 0x82u},
{0x1Au, 0x01u},
{0x1Bu, 0x28u},
{0x1Cu, 0x01u},
{0x1Du, 0x49u},
{0x1Fu, 0x14u},
{0x21u, 0x80u},
{0x22u, 0x02u},
{0x23u, 0x10u},
{0x25u, 0x01u},
{0x26u, 0x04u},
{0x27u, 0x2Au},
{0x29u, 0x02u},
{0x2Du, 0x80u},
{0x2Fu, 0x14u},
{0x35u, 0x01u},
{0x37u, 0x28u},
{0x39u, 0x40u},
{0x3Du, 0x20u},
{0x3Fu, 0x80u},
{0x80u, 0x04u},
{0x81u, 0x50u},
{0x83u, 0x40u},
{0x86u, 0x08u},
{0x87u, 0x08u},
{0x88u, 0x02u},
{0x8Au, 0x02u},
{0x8Bu, 0x20u},
{0x8Cu, 0x05u},
{0x90u, 0x0Cu},
{0x92u, 0x10u},
{0x9Bu, 0x04u},
{0x9Cu, 0x02u},
{0x9Fu, 0x02u},
{0xA5u, 0x01u},
{0xA7u, 0x40u},
{0xA9u, 0x21u},
{0xB7u, 0x40u},
{0xC0u, 0xDEu},
{0xC2u, 0xE5u},
{0xC4u, 0x53u},
{0xCAu, 0x71u},
{0xCCu, 0xE0u},
{0xCEu, 0x38u},
{0xE0u, 0x08u},
{0xE4u, 0x01u},
{0xE6u, 0x20u},
{0xEAu, 0x10u},
{0x50u, 0x06u},
{0x55u, 0x02u},
{0x80u, 0x02u},
{0xD4u, 0xA0u},
{0xD6u, 0x20u},
{0xE2u, 0x20u},
{0x0Au, 0x40u},
{0x0Bu, 0x02u},
{0x0Du, 0x88u},
{0x81u, 0x08u},
{0x82u, 0x40u},
{0x83u, 0x01u},
{0x85u, 0x80u},
{0x89u, 0x02u},
{0xA5u, 0x02u},
{0xB4u, 0x04u},
{0xC2u, 0xF0u},
{0xE0u, 0xA0u},
{0xE4u, 0x60u},
{0x59u, 0x04u},
{0x65u, 0x20u},
{0x81u, 0x20u},
{0x82u, 0x01u},
{0x8Eu, 0x10u},
{0xD6u, 0x02u},
{0xD8u, 0x01u},
{0xE6u, 0x08u},
{0x1Au, 0x10u},
{0x1Cu, 0x08u},
{0x57u, 0x08u},
{0x59u, 0x20u},
{0x66u, 0x81u},
{0x68u, 0x08u},
{0x6Du, 0x08u},
{0x73u, 0x10u},
{0x7Bu, 0x80u},
{0x81u, 0x04u},
{0x83u, 0x08u},
{0x87u, 0x10u},
{0x88u, 0x04u},
{0x8Au, 0x80u},
{0x8Bu, 0x80u},
{0x8Cu, 0x08u},
{0x8Du, 0x04u},
{0x96u, 0x10u},
{0x99u, 0x20u},
{0x9Au, 0x01u},
{0x9Du, 0x04u},
{0xC6u, 0x09u},
{0xD4u, 0x03u},
{0xD6u, 0x01u},
{0xD8u, 0x01u},
{0xDAu, 0x03u},
{0xDCu, 0x01u},
{0xDEu, 0x02u},
{0xE0u, 0x01u},
{0xE2u, 0x04u},
{0xE4u, 0x0Eu},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000333u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x3000EE33u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00C80000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0xAA000000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0xC5000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0xC1090000u);
/* TCPWM_CNT1 Starting address: CYDEV_TCPWM_CNT1_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT1_TR_CTRL0), 0x00060030u);
/* TCPWM_CNT2 Starting address: CYDEV_TCPWM_CNT2_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT2_TR_CTRL0), 0x00020080u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT0_BASE), 0x0000000Fu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x000001B6u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x00000008u);
/* IOPINS0_1 Starting address: CYDEV_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT1_BASE), 0x000000F6u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00492000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000006u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT2_BASE), 0x000000D0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00DB6000u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT3_BASE), 0x000000B3u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00DB0DB6u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC2), 0x00000010u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT4_BASE), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000002u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0001u, /* Base address: 0x400F0000 Count: 1 */
0x400F322Eu, /* Base address: 0x400F3200 Count: 46 */
0x400F3323u, /* Base address: 0x400F3300 Count: 35 */
0x400F4107u, /* Base address: 0x400F4100 Count: 7 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x82u, 0x0Fu},
{0x03u, 0x03u},
{0x07u, 0x0Cu},
{0x0Au, 0x08u},
{0x11u, 0x02u},
{0x16u, 0x0Du},
{0x19u, 0x08u},
{0x1Eu, 0x04u},
{0x22u, 0x01u},
{0x2Eu, 0x02u},
{0x30u, 0x04u},
{0x31u, 0x02u},
{0x32u, 0x02u},
{0x33u, 0x08u},
{0x34u, 0x01u},
{0x35u, 0x04u},
{0x36u, 0x08u},
{0x37u, 0x01u},
{0x3Eu, 0x10u},
{0x40u, 0x30u},
{0x41u, 0x05u},
{0x45u, 0xD0u},
{0x46u, 0x02u},
{0x47u, 0x15u},
{0x48u, 0x36u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Du, 0xA0u},
{0x4Fu, 0x04u},
{0x50u, 0x18u},
{0x52u, 0x80u},
{0x54u, 0x07u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x62u, 0xC0u},
{0x64u, 0x40u},
{0x65u, 0x40u},
{0x66u, 0xC0u},
{0x68u, 0xC0u},
{0x6Au, 0xC0u},
{0x6Cu, 0xC0u},
{0x6Eu, 0xC0u},
{0x06u, 0x04u},
{0x0Du, 0x08u},
{0x0Fu, 0x02u},
{0x16u, 0x80u},
{0x17u, 0x40u},
{0x1Du, 0x08u},
{0x1Eu, 0x08u},
{0x1Fu, 0x81u},
{0x24u, 0x40u},
{0x26u, 0x20u},
{0x27u, 0x22u},
{0x36u, 0x20u},
{0x37u, 0x02u},
{0x3Du, 0x08u},
{0x3Fu, 0x02u},
{0x45u, 0x08u},
{0x4Fu, 0x81u},
{0x55u, 0x04u},
{0x56u, 0x84u},
{0x57u, 0x41u},
{0x5Cu, 0x40u},
{0x5Eu, 0x08u},
{0x5Fu, 0x21u},
{0x77u, 0x40u},
{0x83u, 0x80u},
{0x8Fu, 0x01u},
{0xC0u, 0x40u},
{0xC2u, 0xA0u},
{0xC4u, 0x90u},
{0xCCu, 0xA0u},
{0xCEu, 0xC0u},
{0xD0u, 0x40u},
{0xD2u, 0x10u},
{0xD6u, 0xF0u},
{0xE2u, 0x40u},
{0x59u, 0x10u},
{0x63u, 0x08u},
{0x81u, 0x10u},
{0x8Fu, 0x04u},
{0xD4u, 0x80u},
{0xD8u, 0x40u},
{0xE6u, 0x20u},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x03990300u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00EE0000u);
/* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL0), 0x00000000u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x20200000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0xA0A00000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00C36DB6u);
/* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000064u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00DB1DB6u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000020u);
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00C30000u);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x00000030u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00264240u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0001u, /* Base address: 0x400F0000 Count: 1 */
0x400F325Eu, /* Base address: 0x400F3200 Count: 94 */
0x400F3338u, /* Base address: 0x400F3300 Count: 56 */
0x400F4103u, /* Base address: 0x400F4100 Count: 3 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x83u, 0x0Fu},
{0x02u, 0x06u},
{0x03u, 0x08u},
{0x05u, 0x03u},
{0x07u, 0x44u},
{0x0Eu, 0x03u},
{0x0Fu, 0x55u},
{0x12u, 0x01u},
{0x19u, 0x73u},
{0x1Au, 0x02u},
{0x1Bu, 0x0Cu},
{0x1Cu, 0x06u},
{0x1Eu, 0x01u},
{0x21u, 0x73u},
{0x23u, 0x04u},
{0x2Au, 0x05u},
{0x2Du, 0x2Au},
{0x2Fu, 0x44u},
{0x31u, 0x30u},
{0x33u, 0x0Fu},
{0x36u, 0x07u},
{0x37u, 0x40u},
{0x39u, 0x02u},
{0x3Au, 0x80u},
{0x3Bu, 0x08u},
{0x3Fu, 0x41u},
{0x40u, 0x01u},
{0x46u, 0x40u},
{0x49u, 0xFFu},
{0x4Au, 0x07u},
{0x4Bu, 0xFFu},
{0x4Cu, 0x40u},
{0x4Du, 0x20u},
{0x4Eu, 0xF0u},
{0x4Fu, 0x05u},
{0x50u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x61u, 0xA8u},
{0x62u, 0x40u},
{0x63u, 0x20u},
{0x80u, 0x41u},
{0x81u, 0x09u},
{0x82u, 0x0Eu},
{0x83u, 0x10u},
{0x85u, 0x14u},
{0x89u, 0x10u},
{0x8Eu, 0x0Cu},
{0x90u, 0x20u},
{0x93u, 0x03u},
{0x94u, 0x41u},
{0x95u, 0x10u},
{0x96u, 0x06u},
{0x97u, 0x0Cu},
{0x9Cu, 0x80u},
{0x9Du, 0x1Cu},
{0x9Eu, 0x03u},
{0x9Fu, 0x02u},
{0xA1u, 0x0Cu},
{0xA3u, 0x11u},
{0xA6u, 0x08u},
{0xA8u, 0x0Cu},
{0xAAu, 0x43u},
{0xACu, 0x10u},
{0xB0u, 0x0Fu},
{0xB1u, 0x1Fu},
{0xB2u, 0x10u},
{0xB4u, 0x20u},
{0xB6u, 0xC0u},
{0xB8u, 0x80u},
{0xBAu, 0x02u},
{0xBEu, 0x14u},
{0xC0u, 0x34u},
{0xC1u, 0x01u},
{0xC5u, 0xECu},
{0xC7u, 0x0Bu},
{0xC8u, 0x13u},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCEu, 0xF0u},
{0xCFu, 0x44u},
{0xD0u, 0x0Cu},
{0xD4u, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDAu, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0xE6u, 0xC0u},
{0xEAu, 0x40u},
{0xEBu, 0x02u},
{0x01u, 0x80u},
{0x03u, 0x80u},
{0x04u, 0x01u},
{0x05u, 0x40u},
{0x09u, 0x4Au},
{0x0Cu, 0x20u},
{0x0Fu, 0x82u},
{0x10u, 0x21u},
{0x12u, 0x08u},
{0x17u, 0x20u},
{0x18u, 0x01u},
{0x19u, 0x84u},
{0x1Au, 0xC0u},
{0x1Bu, 0x21u},
{0x1Du, 0x40u},
{0x1Fu, 0x80u},
{0x21u, 0x02u},
{0x25u, 0x08u},
{0x27u, 0xA1u},
{0x2Bu, 0x80u},
{0x2Eu, 0x40u},
{0x2Fu, 0x80u},
{0x31u, 0x0Au},
{0x32u, 0x40u},
{0x37u, 0x20u},
{0x38u, 0x09u},
{0x3Au, 0x10u},
{0x3Cu, 0x01u},
{0x3Fu, 0x84u},
{0x41u, 0x08u},
{0x42u, 0x80u},
{0x43u, 0x80u},
{0x44u, 0x40u},
{0x47u, 0x81u},
{0x49u, 0x01u},
{0x4Bu, 0x04u},
{0x50u, 0x04u},
{0x54u, 0x20u},
{0x55u, 0x40u},
{0x56u, 0x90u},
{0x57u, 0x40u},
{0x58u, 0x41u},
{0x59u, 0x25u},
{0x65u, 0x20u},
{0x67u, 0x04u},
{0x8Eu, 0x48u},
{0x8Fu, 0x20u},
{0xC0u, 0x99u},
{0xC2u, 0xDDu},
{0xC4u, 0x47u},
{0xCAu, 0x91u},
{0xCCu, 0x2Bu},
{0xCEu, 0xD7u},
{0xD0u, 0x1Bu},
{0xD6u, 0x0Fu},
{0xE2u, 0x40u},
{0x63u, 0x08u},
{0x8Fu, 0x04u},
{0xD8u, 0x40u},
{0x01u, 0x01u},
{0x10u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x30000000u);
/* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL3 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00000000u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_PC */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x80000000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000080u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00C00000u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
void cyfitter_cfg(void)
{
#ifdef CYGlobalIntDisable
/* Disable interrupts by default. Let user enable if/when they want. */
CYGlobalIntDisable
#endif
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x00u : 0x01u));
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Set Flash Cycles based on newly configured 24.00MHz Bus Clock. */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x80u : 0x81u));
/* Disable DMA channels so they can be configured for chip initialization */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_PHUB_CH0_BASIC_CFG), 0x00u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_PHUB_CH1_BASIC_CFG), 0x00u);
/* Enable analog pulldown switches */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_ANAIF_CFG_MISC_CR0), 0x01u);
/* Enable/Disable Debug functionality based on settings from System DWR */
CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DBG_DBE, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DBG_DBE) | 0x01u));
{
typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYREG_I2C_XCFG), 20u},
{(void CYFAR *)(CYREG_PRT0_DR), 16u},
{(void CYFAR *)(CYREG_PRT4_DR), 48u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT0_BASE), 7u);
CYCONFIGCPY8((void CYFAR *)(CYDEV_PRTDSI_PRT1_BASE), (const void CYFAR *)(BS_IOPORT_1_VAL), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT2_BASE), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT3_BASE), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT4_BASE), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT5_BASE), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT6_BASE), 7u);
CYCONFIGCPY8((void CYFAR *)(CYDEV_PRTDSI_PRT12_BASE), (const void CYFAR *)(BS_IOPORT_7_VAL), 6u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT15_BASE), 7u);
/* Enable digital routing */
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
CYCONFIGCPY8((void CYFAR *)(CYREG_PRT12_DR), (const void CYFAR *)(BS_IOPINS0_7_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT15_DR), (const void CYFAR *)(BS_IOPINS0_8_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT1_DR), (const void CYFAR *)(BS_IOPINS0_1_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DR), (const void CYFAR *)(BS_IOPINS0_2_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DR), (const void CYFAR *)(BS_IOPINS0_3_VAL), 10u);
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
/* Configure alternate active mode */
CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 12u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_STBY_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_STBY_CFG0) & (uint8)~0x02u); /* Disable CPU */
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3003u, /* Base address: 0x400F3000 Count: 3 */
0x400F3106u, /* Base address: 0x400F3100 Count: 6 */
0x400F3302u, /* Base address: 0x400F3300 Count: 2 */
0x400F4008u, /* Base address: 0x400F4000 Count: 8 */
0x400F4105u, /* Base address: 0x400F4100 Count: 5 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4302u, /* Base address: 0x400F4300 Count: 2 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0xD6u, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0x5Cu, 0x40u},
{0x5Fu, 0x20u},
{0x67u, 0x40u},
{0x87u, 0x40u},
{0xD6u, 0x30u},
{0xD8u, 0x80u},
{0xAFu, 0x20u},
{0xB4u, 0x40u},
{0x0Fu, 0x04u},
{0x6Eu, 0x80u},
{0x73u, 0x08u},
{0x86u, 0x40u},
{0xC2u, 0x80u},
{0xDAu, 0x80u},
{0xDCu, 0x20u},
{0xE6u, 0x40u},
{0x23u, 0x08u},
{0x9Fu, 0x08u},
{0xAFu, 0x04u},
{0xC8u, 0x10u},
{0xE8u, 0x40u},
{0x01u, 0x08u},
{0xC0u, 0x08u},
{0xB5u, 0x08u},
{0xEAu, 0x02u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE99u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x0000FFFFu);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x80000000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x00020000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000005u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00200006u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00000001u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT3_BASE), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000DB1u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC2), 0x00000002u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT4_BASE), 0x0000000Du);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000D8Eu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x0000000Du);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0001u, /* Base address: 0x400F0000 Count: 1 */
0x400F3010u, /* Base address: 0x400F3000 Count: 16 */
0x400F3136u, /* Base address: 0x400F3100 Count: 54 */
0x400F3248u, /* Base address: 0x400F3200 Count: 72 */
0x400F3344u, /* Base address: 0x400F3300 Count: 68 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F430Au, /* Base address: 0x400F4300 Count: 10 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x81u, 0x0Fu},
{0x00u, 0x01u},
{0x02u, 0x02u},
{0x10u, 0x04u},
{0x17u, 0x01u},
{0x18u, 0x06u},
{0x19u, 0x01u},
{0x1Au, 0x01u},
{0x23u, 0x01u},
{0x2Cu, 0x04u},
{0x30u, 0x07u},
{0x37u, 0x01u},
{0x3Au, 0x02u},
{0x3Fu, 0x40u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Fu, 0x01u},
{0x03u, 0x40u},
{0x04u, 0x80u},
{0x05u, 0x04u},
{0x06u, 0x84u},
{0x08u, 0x10u},
{0x0Au, 0x40u},
{0x0Cu, 0x10u},
{0x0Eu, 0x92u},
{0x10u, 0x02u},
{0x16u, 0x20u},
{0x17u, 0x19u},
{0x18u, 0x80u},
{0x19u, 0x02u},
{0x1Au, 0x40u},
{0x1Bu, 0x01u},
{0x1Eu, 0x80u},
{0x22u, 0x40u},
{0x26u, 0x80u},
{0x27u, 0x08u},
{0x29u, 0x02u},
{0x2Bu, 0x40u},
{0x2Du, 0x02u},
{0x2Eu, 0x20u},
{0x2Fu, 0x01u},
{0x30u, 0x10u},
{0x31u, 0x14u},
{0x35u, 0x14u},
{0x37u, 0x01u},
{0x3Cu, 0x80u},
{0x3Du, 0x01u},
{0x3Eu, 0x14u},
{0x44u, 0x98u},
{0x47u, 0x40u},
{0x4Du, 0x08u},
{0x4Fu, 0x80u},
{0x54u, 0x82u},
{0x56u, 0x54u},
{0x62u, 0x80u},
{0x63u, 0x01u},
{0x67u, 0x03u},
{0x6Cu, 0x20u},
{0x6Du, 0x41u},
{0x6Eu, 0x16u},
{0x6Fu, 0x11u},
{0x74u, 0x40u},
{0xC0u, 0xF8u},
{0xC2u, 0xFAu},
{0xC4u, 0x71u},
{0xCAu, 0xB1u},
{0xCCu, 0xE6u},
{0xCEu, 0xF0u},
{0xD0u, 0xF0u},
{0xD2u, 0x10u},
{0xD8u, 0x10u},
{0x00u, 0x1Au},
{0x01u, 0x02u},
{0x03u, 0x08u},
{0x04u, 0x13u},
{0x05u, 0x1Du},
{0x06u, 0x04u},
{0x08u, 0x01u},
{0x09u, 0x1Du},
{0x0Au, 0x18u},
{0x0Cu, 0x18u},
{0x0Du, 0x1Du},
{0x0Eu, 0x02u},
{0x10u, 0x02u},
{0x11u, 0x0Du},
{0x13u, 0x10u},
{0x14u, 0x02u},
{0x16u, 0x18u},
{0x19u, 0x02u},
{0x1Bu, 0x04u},
{0x1Cu, 0x1Cu},
{0x1Du, 0x02u},
{0x1Eu, 0x03u},
{0x1Fu, 0x0Du},
{0x20u, 0x1Au},
{0x23u, 0x10u},
{0x24u, 0x18u},
{0x28u, 0x18u},
{0x29u, 0x01u},
{0x2Au, 0x02u},
{0x2Bu, 0x02u},
{0x2Du, 0x1Du},
{0x31u, 0x0Fu},
{0x32u, 0x13u},
{0x34u, 0x0Fu},
{0x35u, 0x10u},
{0x3Au, 0x20u},
{0x3Bu, 0x02u},
{0x3Fu, 0x10u},
{0x54u, 0x40u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x80u, 0x08u},
{0x82u, 0x06u},
{0x84u, 0x08u},
{0x86u, 0x06u},
{0x8Au, 0x04u},
{0x8Eu, 0x01u},
{0x90u, 0x01u},
{0x91u, 0x0Eu},
{0x94u, 0x01u},
{0x95u, 0x03u},
{0x97u, 0x04u},
{0x98u, 0x0Au},
{0x99u, 0x05u},
{0x9Bu, 0x0Au},
{0xA0u, 0x01u},
{0xA4u, 0x01u},
{0xADu, 0x04u},
{0xAFu, 0x09u},
{0xB0u, 0x01u},
{0xB1u, 0x0Fu},
{0xB2u, 0x06u},
{0xB6u, 0x08u},
{0xB9u, 0x02u},
{0xBEu, 0x41u},
{0xD4u, 0x09u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0x00u, 0x08u},
{0x01u, 0x42u},
{0x03u, 0x09u},
{0x05u, 0x14u},
{0x06u, 0x80u},
{0x07u, 0x01u},
{0x0Au, 0x50u},
{0x0Bu, 0x08u},
{0x0Cu, 0x02u},
{0x0Du, 0x01u},
{0x0Eu, 0x10u},
{0x0Fu, 0x02u},
{0x10u, 0x20u},
{0x11u, 0x01u},
{0x15u, 0x01u},
{0x17u, 0x18u},
{0x18u, 0x40u},
{0x19u, 0x41u},
{0x1Bu, 0x08u},
{0x1Cu, 0x08u},
{0x1Du, 0x14u},
{0x1Fu, 0x04u},
{0x21u, 0x02u},
{0x25u, 0x20u},
{0x27u, 0x40u},
{0x2Bu, 0x01u},
{0x2Cu, 0x80u},
{0x2Fu, 0x05u},
{0x31u, 0x16u},
{0x35u, 0x10u},
{0x37u, 0x41u},
{0x39u, 0x01u},
{0x3Bu, 0x02u},
{0x3Cu, 0x80u},
{0x3Eu, 0xD4u},
{0x3Fu, 0x02u},
{0x40u, 0xC0u},
{0x45u, 0x20u},
{0x46u, 0x08u},
{0x59u, 0x29u},
{0x5Au, 0x80u},
{0x61u, 0x40u},
{0x66u, 0x58u},
{0x85u, 0x21u},
{0x8Bu, 0x08u},
{0x91u, 0x41u},
{0x92u, 0x94u},
{0x99u, 0x0Au},
{0x9Au, 0x50u},
{0x9Bu, 0x18u},
{0x9Cu, 0x80u},
{0x9Du, 0x14u},
{0x9Eu, 0x80u},
{0xA0u, 0xE2u},
{0xA3u, 0x01u},
{0xAEu, 0x40u},
{0xB4u, 0x08u},
{0xB5u, 0x04u},
{0xB7u, 0x40u},
{0xC0u, 0xFFu},
{0xC2u, 0xBEu},
{0xC4u, 0x7Cu},
{0xCAu, 0xB8u},
{0xCCu, 0xB7u},
{0xCEu, 0xF0u},
{0xD6u, 0x0Fu},
{0xD8u, 0x78u},
{0xECu, 0x02u},
{0x08u, 0x20u},
{0xC2u, 0x02u},
{0x5Eu, 0x80u},
{0x64u, 0x10u},
{0x8Au, 0x40u},
{0x98u, 0x10u},
{0xACu, 0x10u},
{0xB4u, 0x20u},
{0xD6u, 0x04u},
{0xD8u, 0x01u},
{0xE0u, 0x04u},
{0xEAu, 0x02u},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
CYPACKED typedef struct {
void CYFAR *dest;
const void CYCODE *src;
uint16 size;
} CYPACKED_ATTR cfg_memcpy_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 128u},
{(void CYFAR *)(CYDEV_UDB_P0_ROUTE_BASE), 768u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
/* UDB_0_1_1_CONFIG Address: CYDEV_UDB_P0_U1_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_0_1_1_CONFIG_VAL[] = {
0x04u, 0x40u, 0x00u, 0x00u, 0x07u, 0x40u, 0x38u, 0x00u, 0x60u, 0x00u, 0x00u, 0x40u, 0x56u, 0x40u, 0x09u, 0x00u,
0x01u, 0x40u, 0x00u, 0x00u, 0x00u, 0x03u, 0x04u, 0x3Cu, 0x0Au, 0x15u, 0x10u, 0x6Au, 0x04u, 0x00u, 0x00u, 0x00u,
0x04u, 0x79u, 0x00u, 0x06u, 0x04u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u, 0x00u, 0x60u, 0x00u, 0x02u, 0x00u, 0x0Du,
0x7Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x0Fu, 0x02u, 0x00u, 0x00u, 0xA0u, 0x00u, 0x00u, 0x00u, 0x00u,
0x35u, 0x01u, 0x40u, 0x00u, 0x02u, 0x0Eu, 0xFDu, 0xCBu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
{(void CYFAR *)(CYDEV_UDB_P0_U1_BASE), BS_UDB_0_1_1_CONFIG_VAL, 128u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
/* Copy device configuration data into registers */
for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
{
const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
void * CYDATA destPtr = mc->dest;
const void CYCODE * CYDATA srcPtr = mc->src;
uint16 CYDATA numBytes = mc->size;
CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00EE0000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0300EE03u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000030u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00024000u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00040000u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000041u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00186D86u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000002u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x20000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x30030000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u);
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3216u, /* Base address: 0x400F3200 Count: 22 */
0x400F3319u, /* Base address: 0x400F3300 Count: 25 */
0x400F4005u, /* Base address: 0x400F4000 Count: 5 */
0x400F4113u, /* Base address: 0x400F4100 Count: 19 */
0x400F4306u, /* Base address: 0x400F4300 Count: 6 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x02u, 0x08u},
{0x06u, 0x80u},
{0x0Au, 0x40u},
{0x0Eu, 0x20u},
{0x12u, 0x02u},
{0x16u, 0x04u},
{0x18u, 0xE1u},
{0x1Au, 0x1Eu},
{0x1Eu, 0x01u},
{0x26u, 0x10u},
{0x28u, 0x99u},
{0x2Au, 0x66u},
{0x2Cu, 0x55u},
{0x2Eu, 0xAAu},
{0x36u, 0xFFu},
{0x37u, 0x01u},
{0x3Eu, 0x40u},
{0x3Fu, 0x40u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x05u, 0x01u},
{0x06u, 0x2Au},
{0x0Du, 0x8Au},
{0x0Eu, 0x04u},
{0x14u, 0x20u},
{0x15u, 0x50u},
{0x1Fu, 0x40u},
{0x25u, 0x40u},
{0x6Du, 0x50u},
{0x6Eu, 0x04u},
{0x82u, 0x2Au},
{0x84u, 0x20u},
{0x87u, 0x40u},
{0x89u, 0xC0u},
{0x8Du, 0x01u},
{0xA1u, 0x0Au},
{0xA9u, 0x02u},
{0xB1u, 0x08u},
{0xC0u, 0xF0u},
{0xC2u, 0xF0u},
{0xC4u, 0xE0u},
{0xE2u, 0x04u},
{0xE4u, 0x40u},
{0xE6u, 0x20u},
{0xECu, 0x20u},
{0x00u, 0x80u},
{0x07u, 0x04u},
{0x51u, 0x10u},
{0xC0u, 0xC0u},
{0xD4u, 0x20u},
{0x01u, 0x10u},
{0x03u, 0x40u},
{0x05u, 0x02u},
{0x06u, 0x01u},
{0x4Bu, 0x10u},
{0x81u, 0x02u},
{0x83u, 0x40u},
{0x85u, 0x10u},
{0x87u, 0x10u},
{0x89u, 0x10u},
{0x8Eu, 0x01u},
{0x95u, 0x20u},
{0xABu, 0x04u},
{0xB0u, 0x40u},
{0xC0u, 0xF0u},
{0xD2u, 0x10u},
{0xE2u, 0x10u},
{0xE4u, 0xB0u},
{0xE8u, 0x80u},
{0x00u, 0x08u},
{0x04u, 0x04u},
{0x80u, 0x04u},
{0x88u, 0x04u},
{0xC0u, 0x0Cu},
{0xE2u, 0x04u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00990067u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x000000EEu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL6), 0x00000800u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x00A00000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00500000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x00AA0000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0xA00A0000u);
/* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000EEE1Eu);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT0_BASE), 0x00000023u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x001B1C40u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC2), 0x00000023u);
/* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000080u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00000249u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000080u);
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x0000003Fu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00180000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x0000003Fu);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x004B6D8Eu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_INTR_CFG), 0x0000F000u);
/* IOPINS0_4 Starting address: CYDEV_GPIO_PRT4_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT4_BASE), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT4_PC), 0x001B6024u);
/* IOPINS0_6 Starting address: CYDEV_GPIO_PRT6_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT6_BASE), 0x00000004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT6_PC), 0x000300C0u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F4003u, /* Base address: 0x400F4000 Count: 3 */
0x400F4105u, /* Base address: 0x400F4100 Count: 5 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x00u, 0x08u},
{0x04u, 0x02u},
{0xC0u, 0x30u},
{0x48u, 0x04u},
{0x4Cu, 0x01u},
{0x90u, 0x02u},
{0xA0u, 0x04u},
{0xD2u, 0x30u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000189u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00000006u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000E00F0u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0004u, /* Base address: 0x400F0000 Count: 4 */
0x400F306Eu, /* Base address: 0x400F3000 Count: 110 */
0x400F3139u, /* Base address: 0x400F3100 Count: 57 */
0x400F3227u, /* Base address: 0x400F3200 Count: 39 */
0x400F334Cu, /* Base address: 0x400F3300 Count: 76 */
0x400F400Cu, /* Base address: 0x400F4000 Count: 12 */
0x400F4105u, /* Base address: 0x400F4100 Count: 5 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x80u, 0x38u},
{0x81u, 0x0Fu},
{0x82u, 0x72u},
{0x83u, 0x0Du},
{0x02u, 0x18u},
{0x04u, 0x04u},
{0x06u, 0xA3u},
{0x09u, 0x8Cu},
{0x0Bu, 0x13u},
{0x0Cu, 0x03u},
{0x0Eu, 0x6Cu},
{0x14u, 0x05u},
{0x17u, 0x08u},
{0x18u, 0xC7u},
{0x19u, 0x20u},
{0x1Au, 0x30u},
{0x1Bu, 0x43u},
{0x1Fu, 0x0Cu},
{0x20u, 0x0Au},
{0x21u, 0xD1u},
{0x22u, 0xC4u},
{0x23u, 0x0Eu},
{0x26u, 0x20u},
{0x28u, 0x04u},
{0x29u, 0xD1u},
{0x2Au, 0x40u},
{0x2Bu, 0x06u},
{0x30u, 0xE0u},
{0x31u, 0x30u},
{0x33u, 0xC0u},
{0x35u, 0x0Fu},
{0x36u, 0x1Fu},
{0x39u, 0x0Au},
{0x3Au, 0x02u},
{0x3Bu, 0x20u},
{0x3Fu, 0x04u},
{0x40u, 0x03u},
{0x47u, 0x04u},
{0x49u, 0xFFu},
{0x4Au, 0x07u},
{0x4Bu, 0xFFu},
{0x4Cu, 0x40u},
{0x4Du, 0x20u},
{0x4Eu, 0xF0u},
{0x4Fu, 0x05u},
{0x50u, 0x08u},
{0x54u, 0x18u},
{0x56u, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x61u, 0xA8u},
{0x62u, 0x40u},
{0x63u, 0x20u},
{0x80u, 0x13u},
{0x81u, 0x20u},
{0x82u, 0x04u},
{0x84u, 0xE0u},
{0x88u, 0xE0u},
{0x8Bu, 0x04u},
{0x8Cu, 0x40u},
{0x8Eu, 0x20u},
{0x90u, 0x03u},
{0x92u, 0x14u},
{0x94u, 0x20u},
{0x96u, 0xC0u},
{0x98u, 0x80u},
{0x99u, 0x02u},
{0x9Au, 0x20u},
{0x9Bu, 0x09u},
{0xA1u, 0x01u},
{0xA2u, 0x08u},
{0xA3u, 0x0Au},
{0xA4u, 0x13u},
{0xA5u, 0x13u},
{0xA6u, 0x0Cu},
{0xA8u, 0x0Au},
{0xA9u, 0x13u},
{0xAAu, 0x14u},
{0xADu, 0x10u},
{0xAEu, 0x15u},
{0xB0u, 0x10u},
{0xB1u, 0x10u},
{0xB2u, 0xE0u},
{0xB3u, 0x03u},
{0xB4u, 0x0Fu},
{0xB5u, 0x20u},
{0xB7u, 0x0Cu},
{0xBAu, 0x20u},
{0xBEu, 0x01u},
{0xBFu, 0x50u},
{0xC0u, 0x32u},
{0xC1u, 0x01u},
{0xC5u, 0xEBu},
{0xC6u, 0x0Cu},
{0xC8u, 0x07u},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCEu, 0xF0u},
{0xCFu, 0x44u},
{0xD0u, 0x0Cu},
{0xD4u, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDAu, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0xE6u, 0xC0u},
{0xEAu, 0x40u},
{0xEBu, 0x02u},
{0x00u, 0x01u},
{0x02u, 0x11u},
{0x04u, 0x20u},
{0x05u, 0x01u},
{0x06u, 0x22u},
{0x09u, 0x20u},
{0x0Au, 0x20u},
{0x0Eu, 0x18u},
{0x0Fu, 0x80u},
{0x10u, 0x68u},
{0x14u, 0x40u},
{0x15u, 0xA2u},
{0x16u, 0x10u},
{0x18u, 0x01u},
{0x19u, 0x01u},
{0x1Du, 0x10u},
{0x1Eu, 0x50u},
{0x21u, 0x35u},
{0x26u, 0x06u},
{0x27u, 0x2Au},
{0x29u, 0x11u},
{0x2Au, 0x11u},
{0x2Eu, 0x20u},
{0x2Fu, 0xAAu},
{0x30u, 0x68u},
{0x33u, 0x10u},
{0x37u, 0x20u},
{0x39u, 0x20u},
{0x3Du, 0x01u},
{0x3Eu, 0x10u},
{0x41u, 0x04u},
{0x46u, 0x11u},
{0x47u, 0x10u},
{0x48u, 0x20u},
{0x4Du, 0x01u},
{0x4Eu, 0x10u},
{0x50u, 0x08u},
{0x54u, 0x80u},
{0x57u, 0x40u},
{0x5Au, 0x01u},
{0x5Du, 0x01u},
{0x5Eu, 0x40u},
{0x5Fu, 0x18u},
{0x60u, 0x04u},
{0x61u, 0x40u},
{0x63u, 0x40u},
{0x80u, 0x01u},
{0x87u, 0x40u},
{0xC0u, 0xFDu},
{0xC2u, 0x76u},
{0xC4u, 0xFEu},
{0xCAu, 0xF5u},
{0xCCu, 0x2Eu},
{0xCEu, 0xA4u},
{0xD0u, 0x72u},
{0xD6u, 0xF1u},
{0xD8u, 0x0Du},
{0x86u, 0x02u},
{0x8Au, 0x04u},
{0x92u, 0x01u},
{0x96u, 0x01u},
{0xA6u, 0x04u},
{0xAAu, 0x02u},
{0xB0u, 0x01u},
{0xB2u, 0x01u},
{0xB4u, 0x02u},
{0xB6u, 0x04u},
{0xBBu, 0x20u},
{0xBEu, 0x51u},
{0xC0u, 0x46u},
{0xC5u, 0xECu},
{0xC7u, 0x02u},
{0xC8u, 0x13u},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCFu, 0x01u},
{0xD0u, 0x18u},
{0xD2u, 0x80u},
{0xD4u, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDAu, 0x04u},
{0xDBu, 0x04u},
{0xDCu, 0x09u},
{0xDDu, 0x99u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE2u, 0x40u},
{0xE4u, 0x40u},
{0xE5u, 0x40u},
{0xE6u, 0x80u},
{0xE8u, 0x80u},
{0xEAu, 0x80u},
{0xECu, 0x80u},
{0xEEu, 0x80u},
{0x00u, 0x10u},
{0x02u, 0x14u},
{0x04u, 0x42u},
{0x05u, 0x18u},
{0x09u, 0x0Au},
{0x0Eu, 0x1Au},
{0x11u, 0x08u},
{0x12u, 0x08u},
{0x15u, 0x40u},
{0x17u, 0x19u},
{0x18u, 0x04u},
{0x19u, 0x40u},
{0x1Au, 0x60u},
{0x1Cu, 0x50u},
{0x1Du, 0x10u},
{0x1Eu, 0x05u},
{0x1Fu, 0x01u},
{0x22u, 0x20u},
{0x24u, 0x01u},
{0x26u, 0x08u},
{0x27u, 0x44u},
{0x2Cu, 0x10u},
{0x2Eu, 0x04u},
{0x2Fu, 0x01u},
{0x35u, 0x28u},
{0x36u, 0x22u},
{0x37u, 0x44u},
{0x3Du, 0x40u},
{0x3Eu, 0x2Au},
{0x41u, 0x02u},
{0x44u, 0x10u},
{0x46u, 0x04u},
{0x47u, 0x02u},
{0x48u, 0x08u},
{0x49u, 0x05u},
{0x4Cu, 0x01u},
{0x4Du, 0x20u},
{0x4Eu, 0x02u},
{0x50u, 0x08u},
{0x51u, 0x08u},
{0x55u, 0x04u},
{0x56u, 0x10u},
{0x59u, 0x05u},
{0x5Au, 0x40u},
{0x5Cu, 0x01u},
{0x6Cu, 0x10u},
{0x6Fu, 0x2Au},
{0x71u, 0x02u},
{0x76u, 0x2Au},
{0x77u, 0x19u},
{0x82u, 0x10u},
{0x8Eu, 0x21u},
{0x91u, 0x40u},
{0x92u, 0x10u},
{0x94u, 0x24u},
{0x96u, 0x01u},
{0x9Bu, 0x02u},
{0x9Du, 0x40u},
{0xA2u, 0x06u},
{0xA7u, 0x2Au},
{0xA9u, 0x40u},
{0xAAu, 0x02u},
{0xABu, 0x80u},
{0xB0u, 0x80u},
{0xB3u, 0x10u},
{0xB4u, 0x20u},
{0xB5u, 0x40u},
{0xC0u, 0xF6u},
{0xC2u, 0xECu},
{0xC4u, 0xF6u},
{0xCAu, 0x50u},
{0xCCu, 0xF0u},
{0xCEu, 0xF0u},
{0xD0u, 0xE1u},
{0xD2u, 0x34u},
{0xD6u, 0x8Bu},
{0x03u, 0x20u},
{0x5Bu, 0x20u},
{0x6Eu, 0x80u},
{0x71u, 0x10u},
{0x83u, 0x20u},
{0x86u, 0x40u},
{0xC0u, 0x10u},
{0xD4u, 0x80u},
{0xDAu, 0x80u},
{0xDCu, 0x20u},
{0xE2u, 0x80u},
{0xE6u, 0x40u},
{0x81u, 0x10u},
{0x9Du, 0x10u},
{0xABu, 0x20u},
{0xE6u, 0x20u},
{0xECu, 0x20u},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
CYPACKED typedef struct {
void CYFAR *dest;
const void CYCODE *src;
uint16 size;
} CYPACKED_ATTR cfg_memcpy_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 512u},
{(void CYFAR *)(CYDEV_UDB_P1_U1_BASE), 384u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
/* UDB_0_0_1_CONFIG Address: CYDEV_UDB_P1_U0_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_0_0_1_CONFIG_VAL[] = {
0x00u, 0x10u, 0xF3u, 0x00u, 0x1Cu, 0x08u, 0xE3u, 0x00u, 0xF3u, 0x18u, 0x0Cu, 0x00u, 0x0Fu, 0x04u, 0xF0u, 0x80u,
0x00u, 0x00u, 0x00u, 0x03u, 0xC3u, 0x3Cu, 0x00u, 0x42u, 0x82u, 0x7Fu, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x04u,
0x08u, 0x00u, 0x00u, 0x00u, 0x04u, 0x67u, 0x00u, 0x18u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x41u, 0x3Cu, 0x00u, 0x41u,
0x2Cu, 0x80u, 0x1Cu, 0x40u, 0x0Fu, 0x1Fu, 0xC0u, 0x20u, 0x00u, 0x08u, 0x22u, 0x20u, 0x00u, 0x00u, 0x00u, 0x40u,
0x35u, 0x06u, 0x02u, 0x00u, 0x04u, 0x00u, 0xE0u, 0x0Cu, 0x18u, 0xFFu, 0xFFu, 0xFFu, 0x62u, 0xA0u, 0xF0u, 0x41u,
0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x13u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x02u, 0x00u, 0x10u, 0x30u, 0x10u, 0x00u, 0x10u, 0x10u, 0x12u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
{(void CYFAR *)(CYDEV_UDB_P1_U0_BASE), BS_UDB_0_0_1_CONFIG_VAL, 128u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
/* Copy device configuration data into registers */
for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
{
const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
void * CYDATA destPtr = mc->dest;
const void CYCODE * CYDATA srcPtr = mc->src;
uint16 CYDATA numBytes = mc->size;
CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000030u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000031u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000C36u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x00020000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00080000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000005u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000006u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
void cyfitter_cfg(void)
{
#ifdef CYGlobalIntDisable
/* Disable interrupts by default. Let user enable if/when they want. */
CYGlobalIntDisable
#endif
/* Enable/Disable Debug functionality based on settings from System DWR */
CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));
{
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
{(void CYFAR *)(CYREG_PRT0_DR), 32u},
{(void CYFAR *)(CYREG_PRT3_DR), 32u},
{(void CYFAR *)(CYREG_PRT12_DR), 16u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_LUT0_CR), 0x0003u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_LUT1_CR), 0x0103u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_LUT3_CR), 0x0303u);
/* Enable digital routing */
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
CYCONFIGCPY((void CYFAR *)(CYREG_PRT15_DR), (const void CYFAR *)(BS_IOPINS0_8_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DR), (const void CYFAR *)(BS_IOPINS0_2_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DM0), (const void CYFAR *)(BS_IOPINS0_5_VAL), 8u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DR), (const void CYFAR *)(BS_IOPINS0_6_VAL), 10u);
/* Switch Boost to the precision bandgap reference from its internal reference */
CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Set Flash Cycles based on newly configured 12.00MHz Bus Clock. */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x41u : 0x40u));
CY_SET_XTND_REG8((void CYFAR *)(CYREG_PANTHER_WAITPIPE), 0x01u);
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
/* Configure alternate active mode */
CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4303u, /* Base address: 0x400F4300 Count: 3 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x0Cu, 0x10u},
{0xC2u, 0x01u},
{0x58u, 0x10u},
{0x98u, 0x10u},
{0xD4u, 0x01u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00000003u);
/* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL0), 0x00000000u);
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_PC */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00000000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x80000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x00020000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x00000081u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00400000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_INTR_CFG), 0x00008000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC2), 0x00000001u);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x000000C1u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00D80006u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u);
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0001u, /* Base address: 0x400F0000 Count: 1 */
0x400F322Cu, /* Base address: 0x400F3200 Count: 44 */
0x400F3323u, /* Base address: 0x400F3300 Count: 35 */
0x400F4104u, /* Base address: 0x400F4100 Count: 4 */
0x400F4307u, /* Base address: 0x400F4300 Count: 7 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x83u, 0x0Du},
{0x8Bu, 0x02u},
{0x8Cu, 0x01u},
{0x8Fu, 0x01u},
{0x91u, 0x04u},
{0x94u, 0x08u},
{0x9Au, 0x04u},
{0xA3u, 0x02u},
{0xA6u, 0x07u},
{0xB0u, 0x02u},
{0xB2u, 0x04u},
{0xB3u, 0x02u},
{0xB4u, 0x08u},
{0xB5u, 0x01u},
{0xB6u, 0x01u},
{0xB7u, 0x04u},
{0xBEu, 0x10u},
{0xBFu, 0x44u},
{0xC0u, 0x20u},
{0xC1u, 0x05u},
{0xC5u, 0xD1u},
{0xC7u, 0x20u},
{0xC8u, 0x23u},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCDu, 0xA0u},
{0xCFu, 0x04u},
{0xD0u, 0x18u},
{0xD2u, 0x80u},
{0xD4u, 0x05u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDAu, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE2u, 0xC0u},
{0xE4u, 0x40u},
{0xE5u, 0x40u},
{0xE6u, 0xC0u},
{0xE8u, 0xC0u},
{0xEAu, 0xC0u},
{0xECu, 0xC0u},
{0xEEu, 0xC0u},
{0x00u, 0x40u},
{0x09u, 0x20u},
{0x0Au, 0x10u},
{0x10u, 0x20u},
{0x18u, 0x44u},
{0x19u, 0x40u},
{0x1Au, 0x10u},
{0x21u, 0x30u},
{0x22u, 0x04u},
{0x23u, 0x01u},
{0x2Au, 0x01u},
{0x33u, 0x01u},
{0x39u, 0x20u},
{0x3Bu, 0x40u},
{0x41u, 0x10u},
{0x48u, 0x22u},
{0x49u, 0x01u},
{0x50u, 0x02u},
{0x52u, 0x01u},
{0x59u, 0x41u},
{0x5Au, 0x08u},
{0x73u, 0x40u},
{0x83u, 0x01u},
{0x87u, 0x01u},
{0x8Cu, 0x04u},
{0xC0u, 0x01u},
{0xC2u, 0x06u},
{0xC4u, 0x04u},
{0xCAu, 0x01u},
{0xCCu, 0x01u},
{0xCEu, 0x0Cu},
{0xD0u, 0x04u},
{0xD2u, 0x08u},
{0xD6u, 0x0Bu},
{0xE2u, 0x02u},
{0x6Cu, 0x20u},
{0x80u, 0x20u},
{0xDAu, 0x80u},
{0xE2u, 0x80u},
{0x07u, 0x80u},
{0x54u, 0x02u},
{0x87u, 0x80u},
{0x8Cu, 0x02u},
{0xC0u, 0x04u},
{0xD6u, 0x04u},
{0xE4u, 0x02u},
{0x01u, 0x01u},
{0x10u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE9900EEu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00003000u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x00C00000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x00000002u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT0_BASE), 0x00000023u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00DB1DA4u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC2), 0x00000020u);
/* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000090u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x009B6006u);
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x00000021u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x0003618Au);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x0000000Fu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00036C90u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC2), 0x00000001u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3101u, /* Base address: 0x400F3100 Count: 1 */
0x400F3303u, /* Base address: 0x400F3300 Count: 3 */
0x400F4008u, /* Base address: 0x400F4000 Count: 8 */
0x400F4107u, /* Base address: 0x400F4100 Count: 7 */
0x400F4201u, /* Base address: 0x400F4200 Count: 1 */
0x400F430Bu, /* Base address: 0x400F4300 Count: 11 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0xE2u, 0x02u},
{0xE2u, 0x01u},
{0xE6u, 0x20u},
{0xEEu, 0x02u},
{0x52u, 0x20u},
{0x56u, 0x80u},
{0x5Bu, 0x20u},
{0x5Fu, 0x80u},
{0x87u, 0x20u},
{0xD4u, 0xE0u},
{0xD6u, 0x20u},
{0xE2u, 0x40u},
{0x83u, 0x80u},
{0x8Au, 0x80u},
{0x9Eu, 0x80u},
{0x9Fu, 0x80u},
{0xAEu, 0x20u},
{0xE2u, 0x80u},
{0xEEu, 0x40u},
{0x86u, 0x04u},
{0x18u, 0x01u},
{0x1Bu, 0x08u},
{0x1Cu, 0x80u},
{0x1Eu, 0x04u},
{0x80u, 0x01u},
{0x88u, 0x40u},
{0x96u, 0x04u},
{0xA7u, 0x08u},
{0xAFu, 0x08u},
{0xC6u, 0x0Fu},
{0xE6u, 0x04u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00003333u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000009u);
/* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL3 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00000000u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_PC */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000000u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00870000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT0_BASE), 0x0000000Fu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000DB6u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000001u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0002u, /* Base address: 0x400F0000 Count: 2 */
0x400F3237u, /* Base address: 0x400F3200 Count: 55 */
0x400F3323u, /* Base address: 0x400F3300 Count: 35 */
0x400F4002u, /* Base address: 0x400F4000 Count: 2 */
0x400F4103u, /* Base address: 0x400F4100 Count: 3 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4302u, /* Base address: 0x400F4300 Count: 2 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x82u, 0x67u},
{0x83u, 0x7Fu},
{0x00u, 0x04u},
{0x03u, 0x03u},
{0x0Eu, 0x0Cu},
{0x14u, 0x01u},
{0x19u, 0x01u},
{0x1Eu, 0x03u},
{0x2Eu, 0x01u},
{0x30u, 0x08u},
{0x32u, 0x02u},
{0x33u, 0x02u},
{0x34u, 0x04u},
{0x36u, 0x01u},
{0x37u, 0x01u},
{0x3Eu, 0x50u},
{0x3Fu, 0x40u},
{0x40u, 0x14u},
{0x41u, 0x06u},
{0x45u, 0x5Cu},
{0x46u, 0x20u},
{0x47u, 0x0Eu},
{0x48u, 0x3Bu},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Du, 0xA0u},
{0x4Fu, 0x01u},
{0x50u, 0x18u},
{0x52u, 0x80u},
{0x54u, 0x07u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Cu, 0x11u},
{0x5Du, 0x11u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x62u, 0x80u},
{0x64u, 0x40u},
{0x65u, 0x40u},
{0x66u, 0x80u},
{0x68u, 0x40u},
{0x6Au, 0x50u},
{0x6Bu, 0xA8u},
{0x6Cu, 0x40u},
{0x6Du, 0x20u},
{0x6Eu, 0x50u},
{0x6Fu, 0xA8u},
{0xB8u, 0x20u},
{0xBEu, 0x10u},
{0xD6u, 0x02u},
{0xD8u, 0x04u},
{0xDBu, 0x04u},
{0xDDu, 0x30u},
{0xDFu, 0x01u},
{0x05u, 0x01u},
{0x06u, 0x01u},
{0x0Eu, 0x12u},
{0x17u, 0x40u},
{0x18u, 0x08u},
{0x1Du, 0x81u},
{0x1Eu, 0x18u},
{0x26u, 0x40u},
{0x27u, 0x20u},
{0x37u, 0x20u},
{0x3Eu, 0x20u},
{0x3Fu, 0x12u},
{0x45u, 0x82u},
{0x4Cu, 0x04u},
{0x4Fu, 0x06u},
{0x55u, 0x02u},
{0x56u, 0x29u},
{0x5Eu, 0x88u},
{0x5Fu, 0x10u},
{0x66u, 0x08u},
{0x67u, 0x04u},
{0x72u, 0x80u},
{0x77u, 0x40u},
{0x82u, 0x80u},
{0xA2u, 0x01u},
{0xB6u, 0x01u},
{0xC0u, 0x90u},
{0xC2u, 0xA0u},
{0xC4u, 0x80u},
{0xCCu, 0x20u},
{0xCEu, 0x80u},
{0xD0u, 0x90u},
{0xD2u, 0x20u},
{0xD6u, 0x70u},
{0xD8u, 0x60u},
{0x6Fu, 0x04u},
{0xDAu, 0x80u},
{0x83u, 0x04u},
{0x9Fu, 0x04u},
{0xE2u, 0x80u},
{0x09u, 0x01u},
{0xC2u, 0x08u},
{0xB5u, 0x01u},
{0xEAu, 0x08u},
{0x10u, 0x0Au},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0A00u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x00800000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x02000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000002u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x0000002Au);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x000319B6u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_INTCFG), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x00000020u);
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00180DB6u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000080u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00D81D80u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC2), 0x00000003u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00C00D80u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000002u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3038u, /* Base address: 0x400F3000 Count: 56 */
0x400F3138u, /* Base address: 0x400F3100 Count: 56 */
0x400F3222u, /* Base address: 0x400F3200 Count: 34 */
0x400F3344u, /* Base address: 0x400F3300 Count: 68 */
0x400F400Bu, /* Base address: 0x400F4000 Count: 11 */
0x400F410Fu, /* Base address: 0x400F4100 Count: 15 */
0x400F420Eu, /* Base address: 0x400F4200 Count: 14 */
0x400F4313u, /* Base address: 0x400F4300 Count: 19 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x00u, 0x01u},
{0x03u, 0x0Fu},
{0x04u, 0x01u},
{0x05u, 0x0Fu},
{0x09u, 0x0Fu},
{0x0Au, 0x01u},
{0x0Du, 0x02u},
{0x0Eu, 0x01u},
{0x0Fu, 0x01u},
{0x11u, 0x08u},
{0x12u, 0x01u},
{0x13u, 0x01u},
{0x15u, 0x04u},
{0x16u, 0x01u},
{0x17u, 0x01u},
{0x18u, 0x01u},
{0x19u, 0x0Fu},
{0x1Cu, 0x01u},
{0x1Du, 0x0Fu},
{0x22u, 0x01u},
{0x23u, 0x0Fu},
{0x24u, 0x01u},
{0x25u, 0x0Fu},
{0x2Au, 0x01u},
{0x2Bu, 0x0Fu},
{0x2Eu, 0x01u},
{0x2Fu, 0x0Fu},
{0x32u, 0x01u},
{0x35u, 0x01u},
{0x37u, 0x0Eu},
{0x38u, 0x08u},
{0x39u, 0xA0u},
{0x3Eu, 0x04u},
{0x3Fu, 0x50u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Fu, 0x01u},
{0x84u, 0x01u},
{0x85u, 0x08u},
{0x89u, 0x04u},
{0x98u, 0x02u},
{0x99u, 0x01u},
{0xACu, 0x04u},
{0xADu, 0x02u},
{0xB0u, 0x02u},
{0xB1u, 0x04u},
{0xB2u, 0x04u},
{0xB3u, 0x02u},
{0xB4u, 0x01u},
{0xB5u, 0x08u},
{0xB7u, 0x01u},
{0xD8u, 0x0Bu},
{0xD9u, 0x0Bu},
{0xDBu, 0x04u},
{0xDCu, 0x99u},
{0xDFu, 0x01u},
{0x02u, 0x89u},
{0x03u, 0x20u},
{0x05u, 0x08u},
{0x08u, 0x99u},
{0x0Eu, 0x08u},
{0x10u, 0x40u},
{0x12u, 0x02u},
{0x13u, 0x28u},
{0x17u, 0x80u},
{0x19u, 0x04u},
{0x1Eu, 0xA0u},
{0x1Fu, 0x20u},
{0x22u, 0x50u},
{0x24u, 0x84u},
{0x26u, 0x0Au},
{0x27u, 0x09u},
{0x28u, 0x68u},
{0x2Au, 0x80u},
{0x2Bu, 0x24u},
{0x2Du, 0x40u},
{0x30u, 0x91u},
{0x31u, 0x10u},
{0x32u, 0x88u},
{0x33u, 0x01u},
{0x35u, 0x20u},
{0x38u, 0x86u},
{0x3Au, 0x51u},
{0x3Bu, 0x08u},
{0x3Du, 0x20u},
{0x3Eu, 0x04u},
{0x5Du, 0x01u},
{0x5Eu, 0xA0u},
{0x5Fu, 0x04u},
{0x64u, 0x20u},
{0x66u, 0x42u},
{0x67u, 0x08u},
{0x7Fu, 0x80u},
{0x82u, 0x04u},
{0x83u, 0x80u},
{0x84u, 0x01u},
{0x85u, 0x01u},
{0x86u, 0x08u},
{0x87u, 0x04u},
{0x88u, 0x04u},
{0x8Cu, 0x0Cu},
{0x8Eu, 0x02u},
{0x8Fu, 0x04u},
{0xC0u, 0x2Fu},
{0xC2u, 0x4Fu},
{0xC4u, 0x8Fu},
{0xCAu, 0x1Fu},
{0xCCu, 0x2Fu},
{0xCEu, 0x6Fu},
{0xD6u, 0xF0u},
{0xD8u, 0xF0u},
{0xDEu, 0x80u},
{0x01u, 0x08u},
{0x02u, 0x01u},
{0x04u, 0x02u},
{0x05u, 0x04u},
{0x08u, 0x01u},
{0x0Cu, 0x04u},
{0x0Du, 0x02u},
{0x14u, 0x08u},
{0x1Cu, 0x01u},
{0x22u, 0x01u},
{0x29u, 0x01u},
{0x2Au, 0x01u},
{0x30u, 0x02u},
{0x31u, 0x01u},
{0x32u, 0x04u},
{0x33u, 0x04u},
{0x34u, 0x08u},
{0x35u, 0x08u},
{0x36u, 0x01u},
{0x37u, 0x02u},
{0x3Eu, 0x40u},
{0x58u, 0x0Bu},
{0x59u, 0x0Bu},
{0x5Bu, 0x04u},
{0x5Cu, 0x99u},
{0x5Fu, 0x01u},
{0x9Cu, 0x01u},
{0xA4u, 0x02u},
{0xB2u, 0x01u},
{0xB4u, 0x02u},
{0xD8u, 0x0Bu},
{0xDBu, 0x04u},
{0xDCu, 0x09u},
{0xDFu, 0x01u},
{0x04u, 0x4Au},
{0x05u, 0x10u},
{0x06u, 0x40u},
{0x0Au, 0x01u},
{0x0Cu, 0x80u},
{0x0Du, 0x80u},
{0x0Fu, 0x10u},
{0x10u, 0x20u},
{0x14u, 0x40u},
{0x17u, 0x20u},
{0x19u, 0x20u},
{0x1Bu, 0x04u},
{0x1Eu, 0xA4u},
{0x1Fu, 0x80u},
{0x25u, 0x28u},
{0x26u, 0x01u},
{0x27u, 0x02u},
{0x2Cu, 0x08u},
{0x3Cu, 0x08u},
{0x3Eu, 0x40u},
{0x3Fu, 0x02u},
{0x45u, 0x28u},
{0x46u, 0x28u},
{0x58u, 0x01u},
{0x59u, 0x04u},
{0x5Au, 0xA0u},
{0x5Bu, 0x02u},
{0x5Du, 0x20u},
{0x5Eu, 0x86u},
{0x64u, 0x01u},
{0x66u, 0x2Au},
{0x7Bu, 0x80u},
{0x7Fu, 0x80u},
{0x80u, 0x80u},
{0x86u, 0x92u},
{0x87u, 0x20u},
{0x88u, 0x40u},
{0x89u, 0x80u},
{0x8Au, 0x50u},
{0x8Du, 0x10u},
{0x90u, 0x48u},
{0x92u, 0xE1u},
{0x93u, 0x10u},
{0x94u, 0x02u},
{0x99u, 0x04u},
{0x9Cu, 0xC0u},
{0x9Du, 0x10u},
{0x9Eu, 0x90u},
{0x9Fu, 0x20u},
{0xA0u, 0x2Cu},
{0xA3u, 0x01u},
{0xA4u, 0x80u},
{0xA7u, 0x84u},
{0xA9u, 0x70u},
{0xADu, 0x08u},
{0xAEu, 0x05u},
{0xB0u, 0x20u},
{0xB3u, 0x11u},
{0xB4u, 0x40u},
{0xB6u, 0x40u},
{0xC0u, 0xF0u},
{0xC2u, 0xA1u},
{0xC4u, 0x54u},
{0xCAu, 0x20u},
{0xCEu, 0xD0u},
{0xD6u, 0xFEu},
{0xD8u, 0xF0u},
{0xDEu, 0x81u},
{0x03u, 0x88u},
{0x05u, 0x10u},
{0x07u, 0x20u},
{0x0Au, 0x18u},
{0x0Cu, 0x80u},
{0x0Du, 0x08u},
{0x83u, 0xA0u},
{0xC0u, 0xF0u},
{0xC2u, 0xF0u},
{0xE0u, 0x80u},
{0xE4u, 0x20u},
{0x02u, 0x10u},
{0x05u, 0x04u},
{0x81u, 0x04u},
{0x86u, 0x10u},
{0xA9u, 0x10u},
{0xAAu, 0x10u},
{0xABu, 0x08u},
{0xACu, 0x80u},
{0xADu, 0x08u},
{0xAEu, 0x04u},
{0xC0u, 0x30u},
{0xE0u, 0x40u},
{0xE4u, 0x80u},
{0xE8u, 0xD0u},
{0xECu, 0xB0u},
{0x00u, 0x20u},
{0x02u, 0x20u},
{0x06u, 0x80u},
{0x07u, 0x04u},
{0x08u, 0x20u},
{0x09u, 0x04u},
{0x0Fu, 0x48u},
{0x8Bu, 0x40u},
{0x8Eu, 0x20u},
{0x8Fu, 0x04u},
{0xC0u, 0x0Fu},
{0xC2u, 0x0Fu},
{0xE2u, 0x0Cu},
{0xE6u, 0x08u},
{0x01u, 0x08u},
{0x06u, 0x80u},
{0x08u, 0x20u},
{0x0Bu, 0x20u},
{0x0Eu, 0x01u},
{0x88u, 0x20u},
{0x8Au, 0x81u},
{0x8Bu, 0x10u},
{0x8Du, 0x08u},
{0xB0u, 0x30u},
{0xB2u, 0x80u},
{0xB5u, 0x04u},
{0xB7u, 0x04u},
{0xC0u, 0x0Cu},
{0xC2u, 0x0Bu},
{0xE2u, 0x07u},
{0xE6u, 0x05u},
{0xEAu, 0x03u},
{0xEEu, 0x07u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x0000FFFFu);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x55550000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x24050000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x55550000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0x51050000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x000000FFu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00249249u);
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000044u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x0008ED89u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_INTCFG), 0x00001000u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000FFu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00249249u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00261D89u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x0000000Du);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000D8Eu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x0000000Du);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3004u, /* Base address: 0x400F3000 Count: 4 */
0x400F3101u, /* Base address: 0x400F3100 Count: 1 */
0x400F3303u, /* Base address: 0x400F3300 Count: 3 */
0x400F4107u, /* Base address: 0x400F4100 Count: 7 */
0x400F4203u, /* Base address: 0x400F4200 Count: 3 */
0x400F430Du, /* Base address: 0x400F4300 Count: 13 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x38u, 0x80u},
{0x3Eu, 0x40u},
{0x58u, 0x04u},
{0x5Fu, 0x01u},
{0x18u, 0x01u},
{0xB4u, 0x01u},
{0xE2u, 0x10u},
{0xE6u, 0x08u},
{0x63u, 0x02u},
{0x66u, 0x08u},
{0x87u, 0x01u},
{0x8Eu, 0x08u},
{0xD6u, 0x40u},
{0xD8u, 0x80u},
{0xE6u, 0x10u},
{0x6Cu, 0x40u},
{0x70u, 0x08u},
{0xDCu, 0x03u},
{0x1Au, 0x80u},
{0x22u, 0x80u},
{0x61u, 0x02u},
{0x86u, 0x80u},
{0x8Eu, 0x40u},
{0xA1u, 0x02u},
{0xB4u, 0x48u},
{0xB5u, 0x02u},
{0xC6u, 0x08u},
{0xC8u, 0x08u},
{0xD8u, 0x02u},
{0xE2u, 0x08u},
{0xECu, 0x08u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x03300000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x000000FFu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x000000FFu);
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000061u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00DB0000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000001u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x0000000Fu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x0000000Fu);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x30000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x20000000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xF3u) | 0x04u);
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u);
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3004u, /* Base address: 0x400F3000 Count: 4 */
0x400F3101u, /* Base address: 0x400F3100 Count: 1 */
0x400F3302u, /* Base address: 0x400F3300 Count: 2 */
0x400F4103u, /* Base address: 0x400F4100 Count: 3 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4306u, /* Base address: 0x400F4300 Count: 6 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x3Au, 0xC0u},
{0x58u, 0x04u},
{0x5Cu, 0x09u},
{0x5Fu, 0x01u},
{0x18u, 0x01u},
{0xB4u, 0x01u},
{0xE6u, 0x80u},
{0x5Du, 0x80u},
{0x89u, 0x80u},
{0xD6u, 0x20u},
{0x61u, 0x02u},
{0xD8u, 0x02u},
{0x1Cu, 0x20u},
{0x88u, 0x10u},
{0xB5u, 0x02u},
{0xC6u, 0x04u},
{0xE6u, 0x01u},
{0xECu, 0x08u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x30080000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EEEEu);
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000009u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00000C06u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x00000090u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00C06000u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000DA4u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00030000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x80000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x00000010u);
/* TCPWM_CNT1 Starting address: CYDEV_TCPWM_CNT1_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT1_TR_CTRL0), 0x00000010u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u);
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}