/**
Initialize controllers that must setup at the early stage
Some peripherals must be initialized in Secure World.
For example, some L2x0 requires to be initialized in Secure World
**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
)
{
BEAGLEBOARD_REVISION Revision;
Revision = BeagleBoardGetRevision();
// Set up Pin muxing.
PadConfiguration (Revision);
// Set up system clocking
ClockInit ();
// Turn off the functional clock for Timer 3
MmioAnd32 (CM_FCLKEN_PER, 0xFFFFFFFF ^ CM_ICLKEN_PER_EN_GPT3_ENABLE );
ArmDataSynchronizationBarrier ();
// Clear IRQs
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSynchronizationBarrier ();
return RETURN_SUCCESS;
}
/**
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
@param InterruptType Defines the type of interrupt or exception that
occurred on the processor.This parameter is processor architecture specific.
@param SystemContext A pointer to the processor context when
the interrupt occurred on the processor.
@return None
**/
VOID
EFIAPI
IrqInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 Vector;
HARDWARE_INTERRUPT_HANDLER InterruptHandler;
Vector = MmioRead32 (INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;
// Needed to prevent infinite nesting when Time Driver lowers TPL
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSynchronizationBarrier ();
InterruptHandler = gRegisteredInterruptHandlers[Vector];
if (InterruptHandler != NULL) {
// Call the registered interrupt handler.
InterruptHandler (Vector, SystemContext);
}
// Needed to clear after running the handler
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSynchronizationBarrier ();
}
VOID
EFIAPI
ArmCleanDataCache (
VOID
)
{
ArmDataSynchronizationBarrier ();
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
/**
Signal to the hardware that the End Of Intrrupt state
has been reached.
@param This Instance pointer for this protocol
@param Source Hardware source of the interrupt
@retval EFI_SUCCESS Source interrupt EOI'ed.
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
**/
EFI_STATUS
EFIAPI
EndOfInterrupt (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
IN HARDWARE_INTERRUPT_SOURCE Source
)
{
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSynchronizationBarrier ();
return EFI_SUCCESS;
}
VOID
ArmV7DataCacheOperation (
IN ARM_V7_CACHE_OPERATION DataCacheOperation
)
{
UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts ();
ArmV7AllDataCachesOperation (DataCacheOperation);
ArmDataSynchronizationBarrier ();
if (SavedInterruptState) {
ArmEnableInterrupts ();
}
}
VOID
CacheRangeOperation (
IN VOID *Start,
IN UINTN Length,
IN LINE_OPERATION LineOperation
)
{
UINTN ArmCacheLineLength = ArmDataCacheLineLength();
UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
// Align address (rounding down)
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
UINTN EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
LineOperation(AlignedAddress);
AlignedAddress += ArmCacheLineLength;
}
ArmDataSynchronizationBarrier ();
}
