/*++ Routine Description: Arguments: FileHandle - Handle of the file being invoked. PeiServices - Describes the list of possible PEI Services. Returns: Status - EFI_SUCCESS if the boot mode could be set --*/ EFI_STATUS EFIAPI InitializeCpuPeim ( IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices ) { EFI_STATUS Status; ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi; UINTN ArmCoreCount; ARM_CORE_INFO *ArmCoreInfoTable; // Enable program flow prediction, if supported. ArmEnableBranchPrediction (); // Publish the CPU memory and io spaces sizes BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize)); // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID**)&ArmMpCoreInfoPpi); if (!EFI_ERROR(Status)) { // Build the MP Core Info Table ArmCoreCount = 0; Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable); if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) { // Build MPCore Info HOB BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount); } } return EFI_SUCCESS; }
VOID ArmCpuSetup ( IN UINTN MpId ) { // Enable SWP instructions ArmEnableSWPInstruction (); // Enable program flow prediction, if supported. ArmEnableBranchPrediction (); }
VOID ArmCpuSetup ( IN UINTN MpId ) { // Enable SWP instructions ArmEnableSWPInstruction (); // Enable program flow prediction, if supported. ArmEnableBranchPrediction (); // If MPCore then Enable the SCU if (ArmIsMpCore()) { // Turn on SMP coherency ArmSetAuxCrBit (A5_FEATURE_SMP); } }
VOID ArmCpuSetup ( IN UINTN MpId ) { // Enable SWP instructions ArmEnableSWPInstruction (); // Enable program flow prediction, if supported. ArmEnableBranchPrediction (); // If MPCore then Enable the SCU if (ArmIsMpCore()) { // Signals the Cortex-A9 processor is taking part in coherency ArmSetAuxCrBit (A9_FEATURE_SMP); ArmEnableScu (); } }
VOID CEntryPoint ( IN VOID *MemoryBase, IN UINTN MemorySize, IN VOID *StackBase, IN UINTN StackSize ) { VOID *HobBase; // Build a basic HOB list HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize)); CreateHobList (MemoryBase, MemorySize, HobBase, StackBase); //Set up Pin muxing. PadConfiguration (); // Set up system clocking ClockInit (); // Enable program flow prediction, if supported. ArmEnableBranchPrediction (); // Initialize CPU cache InitCache ((UINT32)MemoryBase, (UINT32)MemorySize); // Add memory allocation hob for relocated FD BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData); // Add the FVs to the hob list BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize)); // Start talking UartInit (); InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); SaveAndSetDebugTimerInterrupt (TRUE); DEBUG ((EFI_D_ERROR, "UART Enabled\n")); // Start up a free running timer so that the timer lib will work TimerInit (); // SEC phase needs to run library constructors by hand. ExtractGuidedSectionLibConstructor (); LzmaDecompressLibConstructor (); // Build HOBs to pass up our version of stuff the DXE Core needs to save space BuildPeCoffLoaderHob (); BuildExtractSectionHob ( &gLzmaCustomDecompressGuid, LzmaGuidedSectionGetInfo, LzmaGuidedSectionExtraction ); // Assume the FV that contains the SEC (our code) also contains a compressed FV. DecompressFirstFv (); // Load the DXE Core and transfer control to it LoadDxeCoreFromFv (NULL, 0); // DXE Core should always load and never return ASSERT (FALSE); }