static int mtk_fm_i2s_awb_pcm_close(struct snd_pcm_substream *substream) { AudDrv_Emi_Clk_Off(); AudDrv_I2S_Clk_Off(); AudDrv_Clk_Off(); return 0; }
static int mtk_soc_pcm_dl2_close(struct snd_pcm_substream *substream) { pr_warn("%s\n", __func__); if (mPrepareDone == true) { /* stop DAC output */ SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false); if (GetI2SDacEnable() == false) SetI2SDacEnable(false); RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL2, substream); EnableAfe(false); mPrepareDone = false; } if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM) AudDrv_Emi_Clk_Off(); AfeControlSramLock(); ClearSramState(mPlaybackSramState); mPlaybackSramState = GetSramState(); AfeControlSramUnLock(); AudDrv_Clk_Off(); return 0; }
static int mtk_mrgrx_awb_pcm_close(struct snd_pcm_substream *substream) { AudDrv_Emi_Clk_Off(); AudDrv_Clk_Off(); AudDrv_ANA_Clk_Off(); return 0; }
static void GetAudioTrimOffset(int channels) { int Buffer_on_value = 0 , Buffer_offl_value = 0, Buffer_offr_value = 0; const int off_counter = 20, on_counter = 20 , Const_DC_OFFSET = 0;//2048; printk("%s channels = %d\n", __func__, channels); // open headphone and digital part AudDrv_Clk_On(); AudDrv_Emi_Clk_On(); OpenAfeDigitaldl1(true); setHpDcCalibration(AUDIO_ANALOG_DEVICE_OUT_HEADSETR, 0); setHpDcCalibration(AUDIO_ANALOG_DEVICE_OUT_HEADSETL, 0); //get DC value when off //Sammodi Todo, need enable this on Rainier #ifdef RAINIER_NEED_CHECK Buffer_offl_value = PMIC_IMM_GetOneChannelValue(AUXADC_HP_L_CHANNEL, off_counter, 0); #endif printk("%s, Buffer_offl_value = %d \n",__func__, Buffer_offl_value); //Sammodi Todo, need enable this #ifdef RAINIER_NEED_CHECK Buffer_offr_value = PMIC_IMM_GetOneChannelValue(AUXADC_HP_R_CHANNEL, off_counter, 0); #endif printk("%s, Buffer_offr_value = %d \n",__func__, Buffer_offr_value); OpenAnalogHeadphone(true); setHpDcCalibrationGain(AUDIO_ANALOG_DEVICE_OUT_HEADSETR,10); // -1dB, (9-(-1) = 10) setHpDcCalibrationGain(AUDIO_ANALOG_DEVICE_OUT_HEADSETL,10); msleep(10); //Sammodi Todo, need enable this #ifdef RAINIER_NEED_CHECK Buffer_on_value = PMIC_IMM_GetOneChannelValue(AUXADC_HP_L_CHANNEL, on_counter, 0); #endif mHplOffset = Buffer_on_value - Buffer_offl_value + Const_DC_OFFSET; printk("%s, Buffer_on_value = %d Buffer_offl_value = %d mHplOffset = %d \n", __func__,Buffer_on_value, Buffer_offl_value, mHplOffset); //Sammodi Todo, need enable this #ifdef RAINIER_NEED_CHECK Buffer_on_value = PMIC_IMM_GetOneChannelValue(AUXADC_HP_R_CHANNEL, on_counter, 0); #endif mHprOffset = Buffer_on_value - Buffer_offr_value + Const_DC_OFFSET; printk("%s, Buffer_on_value = %d Buffer_offr_value = %d mHprOffset = %d \n", __func__,Buffer_on_value, Buffer_offr_value, mHprOffset); OpenAnalogHeadphone(false); OpenAfeDigitaldl1(false); AudDrv_Emi_Clk_Off(); AudDrv_Clk_Off(); }
static int mtk_pcm_I2S0dl1_close(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; printk("%s \n", __func__); if (mPrepareDone == true) { // stop DAC output SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false); if (GetI2SDacEnable() == false) { SetI2SDacEnable(false); } // stop I2S output SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false); if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false) { Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1); //Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);//K2 TODO: fix fm playback then mp3, i2s_con is misconfigured... } RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream); EnableAfe(false); if (mI2S0dl1_hdoutput_control == true) { printk("%s mI2S0dl1_hdoutput_control == %d \n", __func__, mI2S0dl1_hdoutput_control); EnableI2SDivPower(AUDIO_APLL12_DIV2, false); EnableI2SDivPower(AUDIO_APLL12_DIV4, false); //Todo do we need open I2S3? EnableApll(runtime->rate, false); EnableApllTuner(runtime->rate, false); } mPrepareDone = false; } if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM) { AudDrv_Emi_Clk_Off(); } AfeControlSramLock(); ClearSramState(mPlaybackSramState); mPlaybackSramState = GetSramState(); AfeControlSramUnLock(); AudDrv_Clk_Off(); return 0; }
static int mtk_capture_pcm_close(struct snd_pcm_substream *substream) { if(mCaptureUseSram == false) { AudDrv_Emi_Clk_Off(); } if (mCaptureUseSram == true) { ClearSramState(SRAM_STATE_CAPTURE); mCaptureUseSram = false; } AudDrv_ADC_Clk_Off(); AudDrv_Clk_Off(); return 0; }
static int mtk_pcm_fmtx_close(struct snd_pcm_substream *substream) { PRINTK_AUD_FMTX("%s \n", __func__); // mtk_wcn_cmb_stub_audio_ctrl((CMB_STUB_AIF_X)CMB_STUB_AIF_0); if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM) { AudDrv_Emi_Clk_Off(); } AfeControlSramLock(); ClearSramState(mPlaybackSramState); mPlaybackSramState = GetSramState(); AfeControlSramUnLock(); AudDrv_Clk_Off(); return 0; }
static int mtk_pcm_hdmi_close(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; AFE_BLOCK_T *Afe_Block = &(pMemControl->rBlock); if (bHdmiPrepared) { EnableApllTuner(runtime->rate, false); EnableApll(runtime->rate, false); bHdmiPrepared = false; } AudDrv_Emi_Clk_Off(); AudDrv_Clk_Off(); AudDrv_ANA_Clk_Off(); Afe_Block->u4DMAReadIdx = 0; Afe_Block->u4WriteIdx = 0; Afe_Block->u4DataRemained = 0; return 0; }
static int mtk_pcm_I2S0dl1_close(struct snd_pcm_substream *substream) { printk("%s \n", __func__); if (mPrepareDone == true) { // stop DAC output SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false); if (GetI2SDacEnable() == false) { SetI2SDacEnable(false); } // stop I2S output SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false); if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false) { Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1); //Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);//K2 TODO: fix fm playback then mp3, i2s_con is misconfigured... } RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream); EnableAfe(false); mPrepareDone = false; } if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM) { AudDrv_Emi_Clk_Off(); } AfeControlSramLock(); ClearSramState(mPlaybackSramState); mPlaybackSramState = GetSramState(); AfeControlSramUnLock(); AudDrv_Clk_Off(); return 0; }
static int Audio_hdmi_SideGen_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { printk("%s()\n", __func__); if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(HDMI_SIDEGEN)) { printk("return -EINVAL\n"); return -EINVAL; } #ifdef _TDM_8CH_SGEN_TEST mHdmi_sidegen_control = ucontrol->value.integer.value[0]; if (mHdmi_sidegen_control) { uint32 samplerate = 44100; uint32 Channels = 2; uint32 HDMIchaanel = 8; uint32 Tdm_Lrck = 0; uint32 MclkDiv = 0; //Enable Audio Driver Clock AudDrv_Clk_On(); AudDrv_Emi_Clk_On(); //Enable APLL EnableApll(samplerate, true); EnableApllTuner(samplerate, true); //HDMI I2S clock setting MclkDiv = SetCLkMclk(Soc_Aud_HDMI_MCK, samplerate); SetCLkHdmiBclk(MclkDiv, samplerate, 2 , 32); //enable mclk divider EnableSpdifDivPower(AUDIO_APLL_SPDIF_DIV, true); //enable bck divider EnableHDMIDivPower(AUDIO_APLL_HDMI_BCK_DIV, true); //turn on hdmi clk SetHdmiClkOn(); //Set Mem buffer SetHDMIAddress(); copysinewavetohdmi(8); //config hdmi irq SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE, 44100); //config hdmi interface SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_HDMI, AFE_WLEN_16_BIT); //now fix 16bit SetHdmiTdm1Config(44100, AFE_DATA_WLEN_32BIT); SetHdmiTdm2Config(44100); SetHDMIChannels(HDMIchaanel); //config hdmi connection SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I30, Soc_Aud_InterConnectionOutput_O30); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I31, Soc_Aud_InterConnectionOutput_O31); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I30, Soc_Aud_InterConnectionOutput_O32); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I31, Soc_Aud_InterConnectionOutput_O33); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I30, Soc_Aud_InterConnectionOutput_O34); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I31, Soc_Aud_InterConnectionOutput_O35); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I30, Soc_Aud_InterConnectionOutput_O36); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I31, Soc_Aud_InterConnectionOutput_O37); //Enable hdmi Memory Path SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_HDMI, true); //enable irq SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE, true); //enable hdmi out SetHDMIEnable(true); //enable afe EnableAfe(true); //enable TDM SetTDMEnable(HDMIchaanel); } else { uint32 samplerate = 44100; uint32 Channels = 2; uint32 HDMIchaanel = 8; uint32 Tdm_Lrck = 0; uint32 MclkDiv = 0; SetTDMEnable(false); SetHDMIEnable(false); SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE, false); SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_HDMI, false); EnableAfe(false); SetHdmiPcmInterConnection(Soc_Aud_InterCon_DisConnect, HDMIchaanel); SetHdmiClkOff(); EnableSpdifDivPower(AUDIO_APLL_SPDIF_DIV, false); EnableHDMIDivPower(AUDIO_APLL_HDMI_BCK_DIV, false); AudDrv_Emi_Clk_Off(); AudDrv_Clk_Off(); } #endif return 0; }
static void GetAudioTrimOffset(int channels) { int Buffer_on_value = 0 , Buffer_offl_value = 0, Buffer_offr_value = 0; const int off_counter = 20, on_counter = 20 , Const_DC_OFFSET = 2048; printk("%s channels = %d\n", __func__, channels); // open headphone and digital part AudDrv_Clk_On(); AudDrv_Emi_Clk_On(); OpenAfeDigitaldl1(true); switch (channels) { case AUDIO_OFFSET_TRIM_MUX_HPL: case AUDIO_OFFSET_TRIM_MUX_HPR: { OpenTrimBufferHardware(true); setHpGainZero(); break; } default: break; } // Get HPL off offset SetSdmLevel(AUDIO_SDM_LEVEL_MUTE); msleep(1); setOffsetTrimMux(AUDIO_OFFSET_TRIM_MUX_HPL); setOffsetTrimBufferGain(3); EnableTrimbuffer(true); msleep(1); #if MTK_FPGA Buffer_offl_value = PMIC_IMM_GetOneChannelValue(MT6328_AUX_CH9, off_counter, 0); #else Buffer_offl_value = 0; #endif printk("Buffer_offl_value = %d \n", Buffer_offl_value); EnableTrimbuffer(false); // Get HPR off offset SetSdmLevel(AUDIO_SDM_LEVEL_MUTE); setOffsetTrimMux(AUDIO_OFFSET_TRIM_MUX_HPR); setOffsetTrimBufferGain(3); EnableTrimbuffer(true); msleep(5); #if MTK_FPGA Buffer_offr_value = PMIC_IMM_GetOneChannelValue(MT6328_AUX_CH9, off_counter, 0); #else Buffer_offr_value = 0; #endif printk("Buffer_offr_value = %d \n", Buffer_offr_value); EnableTrimbuffer(false); switch (channels) { case AUDIO_OFFSET_TRIM_MUX_HPL: case AUDIO_OFFSET_TRIM_MUX_HPR: { OpenTrimBufferHardware(false); break; } default: break; } // calibrate HPL offset trim setOffsetTrimMux(AUDIO_OFFSET_TRIM_MUX_HPL); setOffsetTrimBufferGain(3); // EnableTrimbuffer(true); // msleep(5); switch (channels) { case AUDIO_OFFSET_TRIM_MUX_HPL: case AUDIO_OFFSET_TRIM_MUX_HPR: { OpenAnalogHeadphone(true); setHpGainZero(); break; } default: break; } EnableTrimbuffer(true); msleep(10); #ifdef CONFIG_MTK_FPGA Buffer_on_value = PMIC_IMM_GetOneChannelValue(MT6328_AUX_CH9, on_counter, 0); #else Buffer_on_value = 0; #endif mHplOffset = Buffer_on_value - Buffer_offl_value + Const_DC_OFFSET; printk("Buffer_on_value = %d Buffer_offl_value = %d mHplOffset = %d \n", Buffer_on_value, Buffer_offl_value, mHplOffset); EnableTrimbuffer(false); // calibrate HPL offset trim setOffsetTrimMux(AUDIO_OFFSET_TRIM_MUX_HPR); setOffsetTrimBufferGain(3); EnableTrimbuffer(true); msleep(10); #ifdef CONFIG_MTK_FPGA Buffer_on_value = PMIC_IMM_GetOneChannelValue(MT6328_AUX_CH9, on_counter, 0); #else Buffer_on_value = 0; #endif mHprOffset = Buffer_on_value - Buffer_offr_value + Const_DC_OFFSET; printk("Buffer_on_value = %d Buffer_offr_value = %d mHprOffset = %d \n", Buffer_on_value, Buffer_offr_value, mHprOffset); switch (channels) { case AUDIO_OFFSET_TRIM_MUX_HPL: case AUDIO_OFFSET_TRIM_MUX_HPR: OpenAnalogHeadphone(false); break; } setOffsetTrimMux(AUDIO_OFFSET_TRIM_MUX_GROUND); EnableTrimbuffer(false); OpenAfeDigitaldl1(false); SetSdmLevel(AUDIO_SDM_LEVEL_NORMAL); AudDrv_Emi_Clk_Off(); AudDrv_Clk_Off(); }
static int mtk_dl1_awb_pcm_close(struct snd_pcm_substream *substream) { AudDrv_Emi_Clk_Off(); return 0; }
static int mtk_pcm_I2S0dl1_close(struct snd_pcm_substream *substream) { pr_debug("%s \n", __func__); if (mPrepareDone == true) { //Flyme { [email protected] Fix low jitter mode issue that sound will be abnormal when the MediaService reboot if (mi2s0_sidegen_control) { SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false); if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false) { if (mI2S0dl1_hdoutput_control == true) { Afe_Set_Reg(AFE_I2S_CON3, 0, 1 << 12); //Clear Low jitter mode setting } Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1); Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1); SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O00); SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O01); EnableAfe(false); } AudDrv_Clk_Off(); mi2s0_sidegen_control = 0; } if (mI2S0dl1_hdoutput_control) { // set APLL clock setting EnableApll1(false); EnableApll2(false); EnableI2SDivPower(AUDIO_APLL1_DIV0, false); EnableI2SDivPower(AUDIO_APLL2_DIV0, false); AudDrv_APLL1Tuner_Clk_Off(); AudDrv_APLL2Tuner_Clk_Off(); mI2S0dl1_hdoutput_control = false; } // } // stop DAC output SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false); if (GetI2SDacEnable() == false) { SetI2SDacEnable(false); } // stop I2S output SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false); if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false) { Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1); Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1); } RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1,substream); EnableAfe(false); mPrepareDone = false; } if(mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM) { AudDrv_Emi_Clk_Off(); } AfeControlSramLock(); ClearSramState(mPlaybackSramState); mPlaybackSramState = GetSramState(); AfeControlSramUnLock(); AudDrv_Clk_Off(); return 0; }