int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long boot_vector;
pr_info("SMP: Booting CPU%d...\n", cpu);
/*
* set synchronisation state between this boot processor
* and the secondary one
*/
spin_lock(&boot_lock);
/* set the reset vector to point to the secondary_startup routine */
boot_vector = virt_to_phys(brcmstb_secondary_startup);
BDEV_WR(BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0 + cpu * 8, boot_vector);
smp_wmb();
flush_cache_all();
/* unhalt the cpu */
BDEV_UNSET(BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG, BIT(cpu));
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
return 0;
}
static void __init init_port(void)
{
unsigned int divisor;
BDEV_WR(UART_REG(UART_LCR), 0x3); /* 8n1 */
BDEV_WR(UART_REG(UART_IER), 0); /* no interrupt */
BDEV_WR(UART_REG(UART_FCR), 0); /* no fifo */
BDEV_WR(UART_REG(UART_MCR), 0x3); /* DTR + RTS */
BDEV_SET(UART_REG(UART_LCR), UART_LCR_DLAB);
#if defined(CONFIG_BRCM_IKOS)
/* Reverse-engineer brcm_base_baud0 from the bootloader's setting */
divisor = (BDEV_RD(UART_REG(UART_DLM)) << 8) |
BDEV_RD(UART_REG(UART_DLL));
brcm_base_baud0 = divisor * BAUD;
#endif
divisor = (brcm_base_baud0 + BAUD/2) / BAUD;
BDEV_WR(UART_REG(UART_DLL), divisor & 0xff);
BDEV_WR(UART_REG(UART_DLM), (divisor >> 8) & 0xff);
BDEV_UNSET(UART_REG(UART_LCR), UART_LCR_DLAB);
}
static int __devinit brcmnanddrv_probe(struct platform_device *pdev)
{
struct brcmnand_platform_data *cfg = pdev->dev.platform_data;
static int csi; // Index into dev/nandInfo array
int cs = cfg->chip_select; // Chip Select
//int i;
int err = 0;
//static int numCSProcessed = 0;
//int lastChip;
struct brcmnand_info* info;
//extern int dev_debug, gdebug;
/* FOr now all devices share the same buffer */
if (!gPageBuffer) {
#ifndef CONFIG_MTD_BRCMNAND_EDU
gPageBuffer = kmalloc(sizeof(struct nand_buffers), GFP_KERNEL);
#else
/* Align on 32B boundary for efficient DMA transfer */
gPageBuffer = kmalloc(sizeof(struct nand_buffers) + 31, GFP_DMA);
#endif
}
if (!gPageBuffer) {
return -ENOMEM;
}
//gPageBuffer = NULL;
info = kmalloc(sizeof(struct brcmnand_info), GFP_KERNEL);
if (!info)
return -ENOMEM;
gNandInfo[csi] = info;
memset(info, 0, sizeof(struct brcmnand_info));
/*
* Since platform_data does not send us the number of NAND chips,
* (until it's too late to be useful), we have to count it
*/
#ifdef BCHP_NAND_CS_NAND_SELECT
{
uint32_t nandSelect;
/* Set NAND_CS_NAND_SELECT if not already set by CFE */
nandSelect = BDEV_RD(BCHP_NAND_CS_NAND_SELECT);
nandSelect |= 0x100 << cs;
BDEV_WR(BCHP_NAND_CS_NAND_SELECT, nandSelect);
if (0 == gNumNand) { /* First CS */
brcmnand_sort_chipSelects(&info->brcmnand);
gNumNand = info->brcmnand.numchips;
}
else { /* Subsequent CS */
brcmnand_sort_chipSelects(&info->brcmnand);
info->brcmnand.numchips = gNumNand;
}
}
#else
/* Version 1.0 and earlier */
info->brcmnand.numchips = gNumNand = 1;
#endif
info->brcmnand.csi = csi;
/* FOr now all devices share the same buffer */
#ifndef CONFIG_MTD_BRCMNAND_EDU
info->brcmnand.buffers = (struct nand_buffers*) gPageBuffer;
#else
/* Align on 32B boundary for efficient DMA transfer */
info->brcmnand.buffers = (struct nand_buffers*) (((unsigned int) gPageBuffer+31) & (~31));
#endif
info->brcmnand.numchips = gNumNand;
info->brcmnand.chip_shift = 0; // Only 1 chip
info->brcmnand.priv = &info->mtd;
info->mtd.name = dev_name(&pdev->dev);
info->mtd.priv = &info->brcmnand;
info->mtd.owner = THIS_MODULE;
/* Enable the following for a flash based bad block table */
info->brcmnand.options |= NAND_USE_FLASH_BBT;
//cs = cfg->chip_select;
//brcmnand_sort_chipSelects(&info->brcmnand);
// Each chip now will have its own BBT (per mtd handle)
// Problem is we don't know how many CS's we get, until its too late
if (brcmnand_scan(&info->mtd, cs, gNumNand)) {
err = -ENXIO;
goto out_free_info;
}
PRINTK("Master size=%08llx\n", info->mtd.size);
#ifdef CONFIG_MTD_PARTITIONS
/* allow cmdlineparts to override the default map */
err = parse_mtd_partitions(&info->mtd, part_probe_types,
&info->parts, 0);
if (err > 0) {
info->nr_parts = err;
} else {
info->parts = cfg->nr_parts ? cfg->parts : NULL;
info->nr_parts = cfg->nr_parts;
}
// Add MTD partition have a dependency on the BBT
if (info->nr_parts) // Primary mtd
brcmnand_add_mtd_partitions(&info->mtd, info->parts, info->nr_parts);
else // subsequent NAND only hold 1 partition, and is a brand new mtd device
brcmnand_add_mtd_device(&info->mtd, csi);
#else
brcmnand_add_mtd_device(&info->mtd, csi);
#endif
PRINTK("After add_partitions: Master size=%08llx\n", info->mtd.size);
dev_set_drvdata(&pdev->dev, info);
csi++;
return 0;
out_free_info:
if (gPageBuffer)
kfree(gPageBuffer);
kfree(info);
return err;
}
void __init arch_init_irq(void)
{
int irq;
mips_cpu_irq_init();
L1_WR_ALL(W0, MASK_SET, 0xffffffff);
L1_WR_ALL(W1, MASK_SET, 0xffffffff);
L1_WR_ALL(W2, MASK_SET, 0xffffffff);
clear_c0_status(ST0_IE | ST0_IM);
/* Set up all L1 IRQs */
for (irq = 1; irq < BRCM_VIRTIRQ_BASE; irq++)
set_irq_chip_and_handler(irq, &brcm_intc_type,
handle_level_irq);
#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS)
/* default affinity: 1 (TP0 only) */
cpumask_clear(irq_default_affinity);
cpumask_set_cpu(0, irq_default_affinity);
#endif
/* enable IRQ2 (this runs on TP0). IRQ3 enabled during TP1 boot. */
set_c0_status(STATUSF_IP2);
#if ! defined(CONFIG_BRCM_SHARED_UART_IRQ)
/* enable non-shared UART interrupts in the L2 */
#if defined(BCHP_IRQ0_UART_IRQEN_uarta_MASK)
/* 3548 style - separate register */
BDEV_WR(BCHP_IRQ0_UART_IRQEN, BCHP_IRQ0_UART_IRQEN_uarta_MASK |
BCHP_IRQ0_UART_IRQEN_uartb_MASK |
BCHP_IRQ0_UART_IRQEN_uartc_MASK);
BDEV_WR(BCHP_IRQ0_IRQEN, 0);
#elif defined(BCHP_IRQ0_IRQEN_uarta_irqen_MASK)
/* 7405 style - shared with L2 */
BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
#if defined(BCHP_IRQ0_IRQEN_uartc_irqen_MASK)
| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
#endif
);
#endif
#if defined(CONFIG_BRCM_HAS_PCU_UARTS)
BDEV_WR(BCHP_TVM_MAIN_INT_CNTL, 0);
BDEV_WR_F(TVM_MAIN_INT_CNTL, MAIN_UART1_INT_EN, 1);
#endif
#else /* CONFIG_BRCM_SHARED_UART_IRQ */
/* Set up all UPG L2 interrupts */
BDEV_WR_RB(BCHP_IRQ0_IRQEN, 0);
for (irq = BRCM_UPG_L2_BASE; irq <= BRCM_UPG_L2_LAST; irq++)
set_irq_chip_and_handler(irq, &brcm_upg_type, handle_level_irq);
#endif /* CONFIG_BRCM_SHARED_UART_IRQ */
#if defined(BCHP_HIF_INTR2_CPU_MASK_SET)
/* mask and clear all HIF L2 interrupts */
BDEV_WR_RB(BCHP_HIF_INTR2_CPU_MASK_SET, 0xffffffff);
BDEV_WR_RB(BCHP_HIF_INTR2_CPU_CLEAR, 0xffffffff);
#endif
}
void __init prom_init(void)
{
#ifdef CONFIG_MIPS_BRCM97XXX
int hasCfeParms = 0;
int res = -1;
char msg[COMMAND_LINE_SIZE];
extern void determineBootFromFlashOrRom(void);
#endif
uart_init(27000000);
/* jipeng - mask out UPG L2 interrupt here */
BDEV_WR(BCHP_IRQ0_IRQEN, 0);
#ifdef CONFIG_TIVO_KONTIKI
board_pinmux_setup();
#endif
/* Fill in platform information */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BRCM_STB;
#ifdef BRCM_SATA_SUPPORTED
brcm_sata_enabled = 1;
#endif
#ifdef BRCM_ENET_SUPPORTED
brcm_enet_enabled = 1;
#endif
#ifdef BRCM_EMAC_1_SUPPORTED
brcm_emac_1_enabled = 1;
#endif
#ifdef BRCM_PCI_SUPPORTED
brcm_pci_enabled = 1;
#endif
#ifdef CONFIG_SMP
brcm_smp_enabled = 1;
#endif
#ifdef CONFIG_MIPS_BCM7118
/* detect 7118RNG board */
if( BDEV_RD(BCHP_CLKGEN_REG_START) == 0x1c )
brcm_sata_enabled = 0;
/* onchip DOCSIS owns the ENET */
brcm_enet_enabled = 0;
#endif
#ifdef CONFIG_MIPS_BCM7405
/* detect 7406 */
if(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) &
BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_MASK)
brcm_sata_enabled = 0;
switch(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) & 0xf) {
case 0x0:
/* 7405/7406 */
break;
case 0x1:
/* 7466 */
brcm_pci_enabled = 0;
brcm_emac_1_enabled = 0;
break;
case 0x3:
/* 7106 */
brcm_emac_1_enabled = 0;
brcm_smp_enabled = 0;
break;
case 0x4:
/* 7205 */
brcm_emac_1_enabled = 0;
break;
}
#endif
#if defined( CONFIG_MIPS_BCM7118 ) || defined( CONFIG_MIPS_BCM7401C0 ) \
|| defined( CONFIG_MIPS_BCM7402C0 ) || defined( CONFIG_MIPS_BCM3563 ) \
|| defined (CONFIG_MIPS_BCM3563C0)
/*need set bus to async mode before enabling the following*/
if(!(read_c0_diag4() & 0x400000))
{
int val=read_c0_diag4();
write_c0_diag4(val | 0x400000);
sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5());
uart_puts(msg);
write_c0_config(0x80008083);
sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1());
uart_puts(msg);
}
/* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */
BDEV_WR(0x0000040c, 0x264);
/* Enable Split Mode (BCHP_MISB_BRIDGE_MISB_SPLIT_MODE) */
BDEV_WR(0x00000410, 0x1);
#elif defined( CONFIG_MIPS_BCM7440A0 )
if(!(read_c0_diag4() & 0x400000))
{
int val=read_c0_diag4();
write_c0_diag4(val | 0x400000);
sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5());
uart_puts(msg);
write_c0_config(0x80008083);
sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1());
uart_puts(msg);
}
/* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */
BDEV_WR(0x0000040c, 0x2803);
#endif
#ifdef CONFIG_TIVO_MOJAVE
if ( cfe_seal != CFE_SEAL ){
goto noncfe;
}
#endif
/* Kernel arguments */
#ifdef CONFIG_MIPS_BRCM97XXX
/* For the 97xxx series STB, process CFE boot parms */
{
int i;
for (i=0; i<MAX_HWADDR; i++) {
gHwAddrs[i] = &privHwAddrs[i][0];
}
}
#ifdef CONFIG_TIVO_KONTIKI
res = get_cfe_boot_parms();
hasCfeParms = (res == 0);
#if 1 /* ###JLF */
if (gNumHwAddrs > 0)
{
printk("%s(): Got CFE MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x\n",
__FUNCTION__,
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5]);
}
#endif
#ifdef BRCM_MEMORY_STRAPS
get_RAM_size();
#else
if(brcm_dram0_size == 0)
brcm_dram0_size = probe_memsize();
#ifndef CONFIG_DISCONTIGMEM
if(brcm_dram0_size > (256 << 20)) {
printk("Extra RAM beyond 256MB ignored. Please "
"use a kernel that supports DISCONTIG.\n");
brcm_dram0_size = 256 << 20;
}
#endif /* CONFIG_DISCONTIGMEM */
#endif /* BRCM_MEMORY_STRAPS */
// Make sure cfeBootParms is not empty or contains all white space
if (hasCfeParms) {
int i;
hasCfeParms = 0;
for (i=0; i < strlen(cfeBootParms); i++) {
if (isspace(cfeBootParms[i])) {
continue;
}
else if (cfeBootParms[i] == '\0') {
break; // and leave hasCfeParms false
}
else {
hasCfeParms = 1;
break;
}
}
}
#else /* if !defined(CONFIG_TIVO_KONTIKI) */
res = get_cfe_boot_parms(cfeBootParms, &gNumHwAddrs, gHwAddrs);
if(gNumHwAddrs <= 0) {
#if !defined(CONFIG_BRCM_PCI_SLAVE)
unsigned int i, mac = FLASH_MACADDR_ADDR, ok = 0;
for(i = 0; i < 3; i++) {
u16 word = readw((void *)mac);
if(word != 0x0000 && word != 0xffff)
ok = 1;
gHwAddrs[0][(i << 1)] = word & 0xff;
gHwAddrs[0][(i << 1) + 1] = word >> 8;
mac += 2;
}
/* display warning for all 00's, all ff's, or multicast */
if(! ok || (gHwAddrs[0][1] & 1)) {
printk(KERN_WARNING
"WARNING: read invalid MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x from flash @ 0x%08x\n",
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5],
FLASH_MACADDR_ADDR);
}
#else
/* PCI slave mode - no EBI/flash available */
u8 fixed_macaddr[] = { 0x00, 0xc0, 0xa8, 0x74, 0x3b, 0x51 };
memcpy(&gHwAddrs[0][0], fixed_macaddr, sizeof(fixed_macaddr));
#endif
gNumHwAddrs = 1;
}
void prom_putchar(char x)
{
while (!(BDEV_RD(UART_REG(UART_LSR)) & UART_LSR_THRE))
;
BDEV_WR(UART_REG(UART_TX), x);
}
void __init prom_init(void)
{
#ifdef CONFIG_MIPS_BRCM97XXX
int hasCfeParms = 0;
int res = -1;
extern void determineBootFromFlashOrRom(void);
#endif
uart_init(27000000);
/* jipeng - mask out UPG L2 interrupt here */
BDEV_WR(BCHP_IRQ0_IRQEN, 0);
board_pinmux_setup();
/* Fill in platform information */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BRCM_STB;
#ifdef BRCM_SATA_SUPPORTED
brcm_sata_enabled = 1;
#endif
#ifdef BRCM_ENET_SUPPORTED
brcm_enet_enabled = 1;
#endif
#ifdef BRCM_EMAC_1_SUPPORTED
brcm_emac_1_enabled = 1;
#endif
#ifdef BRCM_PCI_SUPPORTED
brcm_pci_enabled = 1;
#endif
#ifdef CONFIG_SMP
brcm_smp_enabled = 1;
#endif
#ifdef CONFIG_MIPS_BCM7118
/* detect 7118RNG board */
if( BDEV_RD(BCHP_CLKGEN_REG_START) == 0x1c )
brcm_sata_enabled = 0;
/* onchip DOCSIS owns the ENET */
brcm_enet_enabled = 0;
#endif
#ifdef CONFIG_MIPS_BCM7405
/* detect 7406 */
if(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) &
BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_MASK)
brcm_sata_enabled = 0;
switch(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) & 0xf) {
case 0x0:
/* 7405/7406 */
break;
case 0x1:
/* 7466 */
brcm_pci_enabled = 0;
brcm_emac_1_enabled = 0;
break;
case 0x3:
/* 7106 */
brcm_emac_1_enabled = 0;
brcm_smp_enabled = 0;
break;
case 0x4:
case 0x6:
/* 7205/7213 */
brcm_emac_1_enabled = 0;
break;
}
#endif
#if defined(CONFIG_BMIPS3300)
// Set BIU to async mode
set_c0_brcm_bus_pll(1 << 22);
// Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT)
BDEV_WR(0x0000040c, 0x264);
// Enable Split Mode (BCHP_MISB_BRIDGE_MISB_SPLIT_MODE)
BDEV_WR(0x00000410, 0x1);
#endif
/* Kernel arguments */
#ifdef CONFIG_MIPS_BRCM97XXX
/* For the 97xxx series STB, process CFE boot parms */
{
int i;
for (i=0; i<MAX_HWADDR; i++) {
gHwAddrs[i] = &privHwAddrs[i][0];
}
}
res = get_cfe_boot_parms();
hasCfeParms = (res == 0);
#ifdef BRCM_MEMORY_STRAPS
get_RAM_size();
#else
if(brcm_dram0_size == 0)
brcm_dram0_size = probe_memsize();
#ifndef CONFIG_DISCONTIGMEM
if(brcm_dram0_size > (256 << 20)) {
printk("Extra RAM beyond 256MB ignored. Please "
"use a kernel that supports DISCONTIG.\n");
brcm_dram0_size = 256 << 20;
}
#endif /* CONFIG_DISCONTIGMEM */
#endif /* BRCM_MEMORY_STRAPS */
if(gNumHwAddrs <= 0) {
#if !defined(CONFIG_BRCM_PCI_SLAVE)
unsigned int i, mac = FLASH_MACADDR_ADDR, ok = 0;
for(i = 0; i < 3; i++) {
u16 word = readw((void *)mac);
if(word != 0x0000 && word != 0xffff)
ok = 1;
gHwAddrs[0][(i << 1)] = word & 0xff;
gHwAddrs[0][(i << 1) + 1] = word >> 8;
mac += 2;
}
/* display warning for all 00's, all ff's, or multicast */
if(! ok || (gHwAddrs[0][0] & 1)) {
u8 fixed_macaddr[] = { 0x00,0x00,0xde,0xad,0xbe,0xef };
printk(KERN_WARNING
"WARNING: read invalid MAC address "
"%02x:%02x:%02x:%02x:%02x:%02x from flash @ 0x%08x\n",
gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2],
gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5],
FLASH_MACADDR_ADDR);
memcpy(&gHwAddrs[0][0], fixed_macaddr,
sizeof(fixed_macaddr));
}
#else
/* PCI slave mode - no EBI/flash available */
u8 fixed_macaddr[] = { 0x00, 0xc0, 0xa8, 0x74, 0x3b, 0x51 };
memcpy(&gHwAddrs[0][0], fixed_macaddr, sizeof(fixed_macaddr));
#endif
gNumHwAddrs = 1;
}
